drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
Extension
.h
Size
10702 bytes
Lines
332
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dce_dmcu_shift {
	DMCU_REG_FIELD_LIST(uint8_t);
};

struct dce_dmcu_mask {
	DMCU_REG_FIELD_LIST(uint32_t);
};

struct dce_dmcu_registers {
	uint32_t DMCU_CTRL;
	uint32_t DMCU_STATUS;
	uint32_t DMCU_RAM_ACCESS_CTRL;
	uint32_t DCI_MEM_PWR_STATUS;
	uint32_t DMU_MEM_PWR_CNTL;
	uint32_t DMCU_IRAM_WR_CTRL;
	uint32_t DMCU_IRAM_WR_DATA;

	uint32_t MASTER_COMM_DATA_REG1;
	uint32_t MASTER_COMM_DATA_REG2;
	uint32_t MASTER_COMM_DATA_REG3;
	uint32_t MASTER_COMM_CMD_REG;
	uint32_t MASTER_COMM_CNTL_REG;
	uint32_t SLAVE_COMM_DATA_REG1;
	uint32_t SLAVE_COMM_DATA_REG2;
	uint32_t SLAVE_COMM_DATA_REG3;
	uint32_t SLAVE_COMM_CMD_REG;
	uint32_t SLAVE_COMM_CNTL_REG;
	uint32_t DMCU_IRAM_RD_CTRL;
	uint32_t DMCU_IRAM_RD_DATA;
	uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
	uint32_t SMU_INTERRUPT_CONTROL;
	uint32_t DC_DMCU_SCRATCH;
	uint32_t DMCUB_SCRATCH15;
};

struct dce_dmcu {
	struct dmcu base;
	const struct dce_dmcu_registers *regs;
	const struct dce_dmcu_shift *dmcu_shift;
	const struct dce_dmcu_mask *dmcu_mask;
};

/*******************************************************************
 *   MASTER_COMM_DATA_REG1   Bit position    Data
 *                           7:0	            hyst_frames[7:0]
 *                           14:8	        hyst_lines[6:0]
 *                           15	            RFB_UPDATE_AUTO_EN
 *                           18:16	        phy_num[2:0]
 *                           21:19	        dcp_sel[2:0]
 *                           22	            phy_type
 *                           23	            frame_cap_ind
 *                           26:24	        aux_chan[2:0]
 *                           30:27	        aux_repeat[3:0]
 *                           31:31	        reserved[31:31]
 ******************************************************************/
union dce_dmcu_psr_config_data_reg1 {
	struct {
		unsigned int timehyst_frames:8;                  /*[7:0]*/
		unsigned int hyst_lines:7;                       /*[14:8]*/
		unsigned int rfb_update_auto_en:1;               /*[15:15]*/
		unsigned int dp_port_num:3;                      /*[18:16]*/
		unsigned int dcp_sel:3;                          /*[21:19]*/
		unsigned int phy_type:1;                         /*[22:22]*/
		unsigned int frame_cap_ind:1;                    /*[23:23]*/
		unsigned int aux_chan:3;                         /*[26:24]*/
		unsigned int aux_repeat:4;                       /*[30:27]*/
		unsigned int allow_smu_optimizations:1;         /*[31:31]*/
	} bits;
	unsigned int u32All;
};

/*******************************************************************
 *   MASTER_COMM_DATA_REG2
 *******************************************************************/
union dce_dmcu_psr_config_data_reg2 {
	struct {
		unsigned int dig_fe:3;                  /*[2:0]*/
		unsigned int dig_be:3;                  /*[5:3]*/
		unsigned int skip_wait_for_pll_lock:1;  /*[6:6]*/
		unsigned int reserved:9;                /*[15:7]*/
		unsigned int frame_delay:8;             /*[23:16]*/
		unsigned int smu_phy_id:4;              /*[27:24]*/
		unsigned int num_of_controllers:4;      /*[31:28]*/
	} bits;
	unsigned int u32All;
};

/*******************************************************************
 *   MASTER_COMM_DATA_REG3
 *******************************************************************/

Annotation

Implementation Notes