drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c- Extension
.c- Size
- 10642 bytes
- Lines
- 500
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dce_i2c.hdce_i2c_sw.hinclude/gpio_service_interface.h
Detected Declarations
function filesfunction read_bit_from_ddcfunction write_bit_to_ddcfunction release_engine_dce_swfunction wait_for_scl_high_swfunction write_byte_swfunction read_byte_swfunction stop_sync_swfunction i2c_write_swfunction i2c_read_swfunction start_sync_swfunction dce_i2c_sw_engine_set_speedfunction dce_i2c_sw_engine_acquire_enginefunction dce_i2c_engine_acquire_swfunction dce_i2c_sw_engine_submit_channel_requestfunction dce_i2c_sw_engine_submit_payloadfunction dce_i2c_submit_command_sw
Annotated Snippet
if (!read_bit_from_ddc(ddc_handle, SDA)) {
++retry;
continue;
}
udelay(clock_delay_div_4);
write_bit_to_ddc(ddc_handle, SCL, true);
if (!wait_for_scl_high_sw(ctx, ddc_handle, clock_delay_div_4))
break;
write_bit_to_ddc(ddc_handle, SDA, false);
udelay(clock_delay_div_4);
write_bit_to_ddc(ddc_handle, SCL, false);
udelay(clock_delay_div_4);
return true;
} while (retry <= I2C_SW_RETRIES);
return false;
}
static void dce_i2c_sw_engine_set_speed(
struct dce_i2c_sw *engine,
uint32_t speed)
{
ASSERT(speed);
engine->speed = speed ? speed : DCE_I2C_DEFAULT_I2C_SW_SPEED;
engine->clock_delay = 1000 / engine->speed;
if (engine->clock_delay < 12)
engine->clock_delay = 12;
}
static bool dce_i2c_sw_engine_acquire_engine(
struct dce_i2c_sw *engine,
struct ddc *ddc)
{
enum gpio_result result;
result = dal_ddc_open(ddc, GPIO_MODE_FAST_OUTPUT,
GPIO_DDC_CONFIG_TYPE_MODE_I2C);
if (result != GPIO_RESULT_OK)
return false;
engine->ddc = ddc;
return true;
}
bool dce_i2c_engine_acquire_sw(
struct dce_i2c_sw *dce_i2c_sw,
struct ddc *ddc_handle)
{
uint32_t counter = 0;
bool result;
do {
result = dce_i2c_sw_engine_acquire_engine(
dce_i2c_sw, ddc_handle);
if (result)
break;
/* i2c_engine is busy by VBios, lets wait and retry */
udelay(10);
++counter;
} while (counter < 2);
return result;
}
static void dce_i2c_sw_engine_submit_channel_request(struct dce_i2c_sw *engine,
struct i2c_request_transaction_data *req)
{
struct ddc *ddc = engine->ddc;
uint32_t clock_delay_div_4 = engine->clock_delay >> 2;
/* send sync (start / repeated start) */
Annotation
- Immediate include surface: `dce_i2c.h`, `dce_i2c_sw.h`, `include/gpio_service_interface.h`.
- Detected declarations: `function files`, `function read_bit_from_ddc`, `function write_bit_to_ddc`, `function release_engine_dce_sw`, `function wait_for_scl_high_sw`, `function write_byte_sw`, `function read_byte_sw`, `function stop_sync_sw`, `function i2c_write_sw`, `function i2c_read_sw`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.