drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c- Extension
.c- Size
- 59878 bytes
- Lines
- 2045
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
reg_helper.hcore_types.hlink_encoder.hdce_link_encoder.hstream_encoder.hdc_bios_types.hgpio_service_interface.hdce/dce_11_0_d.hdce/dce_11_0_sh_mask.hdce/dce_11_0_enum.h
Detected Declarations
function link_transmitter_controlfunction link_dac_encoder_controlfunction enable_phy_bypass_modefunction disable_prbs_symbolsfunction disable_prbs_modefunction program_pattern_symbolsfunction set_dp_phy_pattern_d102function set_link_training_completefunction dce110_get_dig_frontendfunction dce110_link_encoder_set_dp_phy_pattern_training_patternfunction setup_panel_modefunction set_dp_phy_pattern_symbol_errorfunction set_dp_phy_pattern_prbs7function set_dp_phy_pattern_80bit_customfunction set_dp_phy_pattern_hbr2_compliance_cp2520_2function dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2function set_dp_phy_pattern_passthrough_modefunction dce60_set_dp_phy_pattern_passthrough_modefunction get_frontend_sourcefunction configure_encoderfunction dce60_configure_encoderfunction aux_initializefunction dce110_psr_program_dp_dphy_fast_trainingfunction dce110_psr_program_secondary_packetfunction dce110_is_dig_enabledfunction link_encoder_disablefunction hpd_initializefunction dce110_link_encoder_validate_dvi_outputfunction dce110_link_encoder_validate_hdmi_outputfunction dce110_link_encoder_validate_dp_outputfunction dce110_link_encoder_validate_rgb_outputfunction dce110_link_encoder_constructfunction dce110_link_encoder_validate_output_with_streamfunction dce110_link_encoder_hw_initfunction dce110_link_encoder_destroyfunction dce110_link_encoder_setupfunction dce110_link_encoder_enable_tmds_outputfunction dce110_link_encoder_enable_lvds_outputfunction dce110_link_encoder_enable_analog_outputfunction dce110_link_encoder_enable_dp_outputfunction dce110_link_encoder_enable_dp_mst_outputfunction dce60_link_encoder_enable_dp_outputfunction dce60_link_encoder_enable_dp_mst_outputfunction dce110_link_encoder_disable_outputfunction dce110_link_encoder_dp_set_lane_settingsfunction dce110_link_encoder_dp_set_phy_patternfunction dce60_link_encoder_dp_set_phy_patternfunction fill_stream_allocation_row_info
Annotated Snippet
if (init_data->analog_engine != ENGINE_ID_UNKNOWN) {
/* The connector is analog-only, ie. VGA */
enc110->base.preferred_engine = init_data->analog_engine;
enc110->base.output_signals = SIGNAL_TYPE_RGB;
enc110->base.transmitter = TRANSMITTER_UNKNOWN;
break;
}
ASSERT_CRITICAL(false);
enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
}
/* default to one to mirror Windows behavior */
enc110->base.features.flags.bits.HDMI_6GB_EN = 1;
result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios,
enc110->base.id, &bp_cap_info);
/* Override features with DCE-specific values */
if (result == BP_RESULT_OK) {
enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
bp_cap_info.DP_HBR2_EN;
enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
bp_cap_info.DP_HBR3_EN;
enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
} else if (result != BP_RESULT_NORECORD) {
DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
__func__,
result);
}
if (enc110->base.ctx->dc->debug.hdmi20_disable) {
enc110->base.features.flags.bits.HDMI_6GB_EN = 0;
}
}
bool dce110_link_encoder_validate_output_with_stream(
struct link_encoder *enc,
const struct dc_stream_state *stream)
{
struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
bool is_valid;
switch (stream->signal) {
case SIGNAL_TYPE_DVI_SINGLE_LINK:
case SIGNAL_TYPE_DVI_DUAL_LINK:
is_valid = dce110_link_encoder_validate_dvi_output(
enc110,
stream->link->connector_signal,
stream->signal,
&stream->timing);
break;
case SIGNAL_TYPE_HDMI_TYPE_A:
is_valid = dce110_link_encoder_validate_hdmi_output(
enc110,
&stream->timing,
stream->phy_pix_clk);
break;
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_DISPLAY_PORT_MST:
is_valid = dce110_link_encoder_validate_dp_output(
enc110, &stream->timing);
break;
case SIGNAL_TYPE_RGB:
is_valid = dce110_link_encoder_validate_rgb_output(
enc110, &stream->timing);
break;
case SIGNAL_TYPE_EDP:
case SIGNAL_TYPE_LVDS:
is_valid = stream->timing.pixel_encoding == PIXEL_ENCODING_RGB;
break;
case SIGNAL_TYPE_VIRTUAL:
is_valid = true;
break;
default:
is_valid = false;
break;
}
return is_valid;
}
void dce110_link_encoder_hw_init(
struct link_encoder *enc)
{
struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
struct bp_transmitter_control cntl = { 0 };
enum bp_result result;
cntl.action = TRANSMITTER_CONTROL_INIT;
cntl.engine_id = ENGINE_ID_UNKNOWN;
cntl.transmitter = enc110->base.transmitter;
Annotation
- Immediate include surface: `reg_helper.h`, `core_types.h`, `link_encoder.h`, `dce_link_encoder.h`, `stream_encoder.h`, `dc_bios_types.h`, `gpio_service_interface.h`, `dce/dce_11_0_d.h`.
- Detected declarations: `function link_transmitter_control`, `function link_dac_encoder_control`, `function enable_phy_bypass_mode`, `function disable_prbs_symbols`, `function disable_prbs_mode`, `function program_pattern_symbols`, `function set_dp_phy_pattern_d102`, `function set_link_training_complete`, `function dce110_get_dig_frontend`, `function dce110_link_encoder_set_dp_phy_pattern_training_pattern`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.