drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h- Extension
.h- Size
- 18441 bytes
- Lines
- 468
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dc_hw_types.hmem_input.h
Detected Declarations
struct dce_mem_input_registersstruct dce_mem_input_shiftstruct dce_mem_input_maskstruct dce_mem_input_wastruct dce_mem_input
Annotated Snippet
struct dce_mem_input_registers {
/* DCP */
uint32_t GRPH_ENABLE;
uint32_t GRPH_CONTROL;
uint32_t GRPH_X_START;
uint32_t GRPH_Y_START;
uint32_t GRPH_X_END;
uint32_t GRPH_Y_END;
uint32_t GRPH_PITCH;
uint32_t HW_ROTATION;
uint32_t GRPH_SWAP_CNTL;
uint32_t PRESCALE_GRPH_CONTROL;
uint32_t GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT;
uint32_t DVMM_PTE_CONTROL;
uint32_t DVMM_PTE_ARB_CONTROL;
uint32_t GRPH_UPDATE;
uint32_t GRPH_FLIP_CONTROL;
uint32_t GRPH_PRIMARY_SURFACE_ADDRESS;
uint32_t GRPH_PRIMARY_SURFACE_ADDRESS_HIGH;
uint32_t GRPH_SECONDARY_SURFACE_ADDRESS;
uint32_t GRPH_SECONDARY_SURFACE_ADDRESS_HIGH;
/* DMIF_PG */
uint32_t DPG_PIPE_ARBITRATION_CONTROL1;
#if defined(CONFIG_DRM_AMD_DC_SI)
uint32_t DPG_PIPE_ARBITRATION_CONTROL3;
#endif
uint32_t DPG_WATERMARK_MASK_CONTROL;
uint32_t DPG_PIPE_URGENCY_CONTROL;
uint32_t DPG_PIPE_URGENT_LEVEL_CONTROL;
uint32_t DPG_PIPE_NB_PSTATE_CHANGE_CONTROL;
uint32_t DPG_PIPE_LOW_POWER_CONTROL;
uint32_t DPG_PIPE_STUTTER_CONTROL;
uint32_t DPG_PIPE_STUTTER_CONTROL2;
/* DCI */
uint32_t DMIF_BUFFER_CONTROL;
/* MC_HUB */
uint32_t MC_HUB_RDREQ_DMIF_LIMIT;
/*DCHUB*/
uint32_t DCHUB_FB_LOCATION;
uint32_t DCHUB_AGP_BASE;
uint32_t DCHUB_AGP_BOT;
uint32_t DCHUB_AGP_TOP;
};
/* Set_Filed_for_Block */
#define SFB(blk_name, reg_name, field_name, post_fix)\
.field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
#if defined(CONFIG_DRM_AMD_DC_SI)
#define MI_GFX6_TILE_MASK_SH_LIST(mask_sh, blk)\
SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_PIPE_CONFIG, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_ARRAY_MODE, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh)
#endif
#define MI_GFX8_TILE_MASK_SH_LIST(mask_sh, blk)\
SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_PIPE_CONFIG, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_ARRAY_MODE, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh)
#define MI_DCP_MASK_SH_LIST(mask_sh, blk)\
SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\
SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\
SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
SFB(blk, GRPH_Y_END, GRPH_Y_END, mask_sh),\
SFB(blk, GRPH_PITCH, GRPH_PITCH, mask_sh),\
SFB(blk, HW_ROTATION, GRPH_ROTATION_ANGLE, mask_sh),\
SFB(blk, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, mask_sh),\
SFB(blk, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, mask_sh),\
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh),\
SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_SURFACE_ADDRESS, mask_sh),\
Annotation
- Immediate include surface: `dc_hw_types.h`, `mem_input.h`.
- Detected declarations: `struct dce_mem_input_registers`, `struct dce_mem_input_shift`, `struct dce_mem_input_mask`, `struct dce_mem_input_wa`, `struct dce_mem_input`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.