drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c- Extension
.c- Size
- 48105 bytes
- Lines
- 1700
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dce_transform.hreg_helper.hopp.hbasics/conversion.hdc.h
Detected Declarations
enum dcp_out_trunc_round_modeenum dcp_out_trunc_round_depthenum dcp_bit_depth_reduction_modeenum dcp_spatial_dither_modeenum dcp_spatial_dither_depthenum csc_color_modeenum grph_color_adjust_optionfunction setup_scaling_configurationfunction dce60_setup_scaling_configurationfunction program_overscanfunction program_multi_taps_filterfunction program_viewportfunction calculate_initsfunction dce60_calculate_initsfunction program_scl_ratios_initsfunction dce60_program_scl_ratios_initsfunction dce_transform_set_scalerfunction dce60_transform_set_scalerfunction set_clampfunction set_roundfunction set_ditherfunction registersfunction registersfunction dce_transform_get_max_num_of_supported_linesfunction set_denormalizationfunction dce_transform_set_pixel_storage_depthfunction dce60_transform_set_pixel_storage_depthfunction program_gamut_remapfunction dce_transform_set_gamut_remapfunction decide_tapsfunction dce_transform_get_optimal_number_of_tapsfunction dce_transform_resetfunction program_color_matrixfunction configure_graphics_modefunction dce110_opp_set_csc_adjustmentfunction dce110_opp_set_csc_defaultfunction program_pwlfunction regamma_config_regions_and_segmentsfunction dce110_opp_program_regamma_pwlfunction dce110_opp_power_on_regamma_lutfunction dce110_opp_set_regamma_modefunction dce_transform_constructfunction dce60_transform_construct
Annotated Snippet
if (coeffs_v != xfm_dce->filter_v || coeffs_h != xfm_dce->filter_h) {
/* 4. Program vertical filters */
if (xfm_dce->filter_v == NULL)
REG_SET(SCL_VERT_FILTER_CONTROL, 0,
SCL_V_2TAP_HARDCODE_COEF_EN, 0);
program_multi_taps_filter(
xfm_dce,
data->taps.v_taps,
coeffs_v,
FILTER_TYPE_RGB_Y_VERTICAL);
program_multi_taps_filter(
xfm_dce,
data->taps.v_taps,
coeffs_v,
FILTER_TYPE_ALPHA_VERTICAL);
/* 5. Program horizontal filters */
if (xfm_dce->filter_h == NULL)
REG_SET(SCL_HORZ_FILTER_CONTROL, 0,
SCL_H_2TAP_HARDCODE_COEF_EN, 0);
program_multi_taps_filter(
xfm_dce,
data->taps.h_taps,
coeffs_h,
FILTER_TYPE_RGB_Y_HORIZONTAL);
program_multi_taps_filter(
xfm_dce,
data->taps.h_taps,
coeffs_h,
FILTER_TYPE_ALPHA_HORIZONTAL);
xfm_dce->filter_v = coeffs_v;
xfm_dce->filter_h = coeffs_h;
filter_updated = true;
}
}
/* 6. Program the viewport */
program_viewport(xfm_dce, &data->viewport);
/* 7. Set bit to flip to new coefficient memory */
if (filter_updated)
REG_UPDATE(SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, 1);
REG_UPDATE(LB_DATA_FORMAT, ALPHA_EN, data->lb_params.alpha_en);
}
#if defined(CONFIG_DRM_AMD_DC_SI)
static void dce60_transform_set_scaler(
struct transform *xfm,
const struct scaler_data *data)
{
struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
bool is_scaling_required;
const uint16_t *coeffs_v, *coeffs_h;
/*Use whole line buffer memory always*/
REG_SET(DC_LB_MEMORY_SPLIT, 0,
DC_LB_MEMORY_CONFIG, 0);
REG_SET(DC_LB_MEM_SIZE, 0,
DC_LB_MEM_SIZE, xfm_dce->lb_memory_size);
REG_WRITE(SCL_UPDATE, 0x00010000);
/* Clear SCL_F_SHARP_CONTROL value to 0 */
REG_WRITE(SCL_F_SHARP_CONTROL, 0);
/* 1. Program overscan */
program_overscan(xfm_dce, data);
/* 2. Program taps and configuration */
is_scaling_required = dce60_setup_scaling_configuration(xfm_dce, data);
if (is_scaling_required) {
/* 3. Calculate and program ratio, DCE6 filter initialization */
struct sclh_ratios_inits inits = { 0 };
/* DCE6 has specific calculate_inits() function */
dce60_calculate_inits(xfm_dce, data, &inits);
/* DCE6 has specific program_scl_ratios_inits() function */
dce60_program_scl_ratios_inits(xfm_dce, &inits);
coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, data->ratios.vert);
coeffs_h = get_filter_coeffs_16p(data->taps.h_taps, data->ratios.horz);
if (coeffs_v != xfm_dce->filter_v || coeffs_h != xfm_dce->filter_h) {
/* 4. Program vertical filters */
if (xfm_dce->filter_v == NULL)
Annotation
- Immediate include surface: `dce_transform.h`, `reg_helper.h`, `opp.h`, `basics/conversion.h`, `dc.h`.
- Detected declarations: `enum dcp_out_trunc_round_mode`, `enum dcp_out_trunc_round_depth`, `enum dcp_bit_depth_reduction_mode`, `enum dcp_spatial_dither_mode`, `enum dcp_spatial_dither_depth`, `enum csc_color_mode`, `enum grph_color_adjust_option`, `function setup_scaling_configuration`, `function dce60_setup_scaling_configuration`, `function program_overscan`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.