drivers/gpu/drm/amd/display/dc/dce/dce_transform.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dce/dce_transform.h
Extension
.h
Size
30331 bytes
Lines
700
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dce_transform_shift {
	XFM_REG_FIELD_LIST(uint8_t);
};

struct dce_transform_mask {
	XFM_REG_FIELD_LIST(uint32_t);
};

struct dce_transform_registers {
#if defined(CONFIG_DRM_AMD_DC_SI)
	uint32_t DATA_FORMAT;
#endif
	uint32_t LB_DATA_FORMAT;
	uint32_t GAMUT_REMAP_CONTROL;
	uint32_t GAMUT_REMAP_C11_C12;
	uint32_t GAMUT_REMAP_C13_C14;
	uint32_t GAMUT_REMAP_C21_C22;
	uint32_t GAMUT_REMAP_C23_C24;
	uint32_t GAMUT_REMAP_C31_C32;
	uint32_t GAMUT_REMAP_C33_C34;
	uint32_t OUTPUT_CSC_C11_C12;
	uint32_t OUTPUT_CSC_C13_C14;
	uint32_t OUTPUT_CSC_C21_C22;
	uint32_t OUTPUT_CSC_C23_C24;
	uint32_t OUTPUT_CSC_C31_C32;
	uint32_t OUTPUT_CSC_C33_C34;
	uint32_t OUTPUT_CSC_CONTROL;
	uint32_t DCFE_MEM_LIGHT_SLEEP_CNTL;
	uint32_t REGAMMA_CNTLA_START_CNTL;
	uint32_t REGAMMA_CNTLA_SLOPE_CNTL;
	uint32_t REGAMMA_CNTLA_END_CNTL1;
	uint32_t REGAMMA_CNTLA_END_CNTL2;
	uint32_t REGAMMA_CNTLA_REGION_0_1;
	uint32_t REGAMMA_CNTLA_REGION_2_3;
	uint32_t REGAMMA_CNTLA_REGION_4_5;
	uint32_t REGAMMA_CNTLA_REGION_6_7;
	uint32_t REGAMMA_CNTLA_REGION_8_9;
	uint32_t REGAMMA_CNTLA_REGION_10_11;
	uint32_t REGAMMA_CNTLA_REGION_12_13;
	uint32_t REGAMMA_CNTLA_REGION_14_15;
	uint32_t REGAMMA_LUT_WRITE_EN_MASK;
	uint32_t REGAMMA_LUT_INDEX;
	uint32_t REGAMMA_LUT_DATA;
	uint32_t REGAMMA_CONTROL;
	uint32_t DENORM_CONTROL;
	uint32_t DCP_SPATIAL_DITHER_CNTL;
	uint32_t OUT_ROUND_CONTROL;
	uint32_t OUT_CLAMP_CONTROL_R_CR;
	uint32_t OUT_CLAMP_CONTROL_G_Y;
	uint32_t OUT_CLAMP_CONTROL_B_CB;
	uint32_t SCL_MODE;
	uint32_t SCL_TAP_CONTROL;
	uint32_t SCL_CONTROL;
	uint32_t SCL_BYPASS_CONTROL;
	uint32_t EXT_OVERSCAN_LEFT_RIGHT;
	uint32_t EXT_OVERSCAN_TOP_BOTTOM;
	uint32_t SCL_VERT_FILTER_CONTROL;
	uint32_t SCL_HORZ_FILTER_CONTROL;
	uint32_t DCFE_MEM_PWR_CTRL;
	uint32_t DCFE_MEM_PWR_STATUS;
	uint32_t SCL_COEF_RAM_SELECT;
	uint32_t SCL_COEF_RAM_TAP_DATA;
	uint32_t VIEWPORT_START;
	uint32_t VIEWPORT_SIZE;
	uint32_t SCL_HORZ_FILTER_SCALE_RATIO;
	uint32_t SCL_VERT_FILTER_SCALE_RATIO;
	uint32_t SCL_HORZ_FILTER_INIT;
#if defined(CONFIG_DRM_AMD_DC_SI)
	uint32_t SCL_SCALER_ENABLE;
	uint32_t SCL_HORZ_FILTER_INIT_RGB_LUMA;
	uint32_t SCL_HORZ_FILTER_INIT_CHROMA;
#endif
	uint32_t SCL_VERT_FILTER_INIT;
	uint32_t SCL_AUTOMATIC_MODE_CONTROL;
#if defined(CONFIG_DRM_AMD_DC_SI)
	uint32_t DC_LB_MEMORY_SPLIT;
	uint32_t DC_LB_MEM_SIZE;
#endif
	uint32_t LB_MEMORY_CTRL;
	uint32_t SCL_UPDATE;
	uint32_t SCL_F_SHARP_CONTROL;
};

struct init_int_and_frac {
	uint32_t integer;
	uint32_t fraction;
};

struct scl_ratios_inits {
	uint32_t h_int_scale_ratio;

Annotation

Implementation Notes