drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h- Extension
.h- Size
- 11342 bytes
- Lines
- 268
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct dcn10_dwbc_registersstruct dcn10_dwbc_maskstruct dcn10_dwbc_shiftstruct dcn10_dwbc
Annotated Snippet
struct dcn10_dwbc_registers {
uint32_t WB_ENABLE;
uint32_t WB_EC_CONFIG;
uint32_t CNV_MODE;
uint32_t WB_SOFT_RESET;
uint32_t MCIF_WB_BUFMGR_SW_CONTROL;
uint32_t MCIF_WB_BUF_PITCH;
uint32_t MCIF_WB_ARBITRATION_CONTROL;
uint32_t MCIF_WB_SCLK_CHANGE;
uint32_t MCIF_WB_BUF_1_ADDR_Y;
uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET;
uint32_t MCIF_WB_BUF_1_ADDR_C;
uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET;
uint32_t MCIF_WB_BUF_2_ADDR_Y;
uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET;
uint32_t MCIF_WB_BUF_2_ADDR_C;
uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET;
uint32_t MCIF_WB_BUF_3_ADDR_Y;
uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET;
uint32_t MCIF_WB_BUF_3_ADDR_C;
uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET;
uint32_t MCIF_WB_BUF_4_ADDR_Y;
uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET;
uint32_t MCIF_WB_BUF_4_ADDR_C;
uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET;
uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;
uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK;
uint32_t MCIF_WB_NB_PSTATE_CONTROL;
uint32_t MCIF_WB_WATERMARK;
uint32_t MCIF_WB_WARM_UP_CNTL;
uint32_t MCIF_WB_BUF_LUMA_SIZE;
uint32_t MCIF_WB_BUF_CHROMA_SIZE;
};
struct dcn10_dwbc_mask {
DWBC_REG_FIELD_LIST(uint32_t)
};
struct dcn10_dwbc_shift {
DWBC_REG_FIELD_LIST(uint8_t)
};
struct dcn10_dwbc {
struct dwbc base;
const struct dcn10_dwbc_registers *dwbc_regs;
const struct dcn10_dwbc_shift *dwbc_shift;
const struct dcn10_dwbc_mask *dwbc_mask;
};
void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
struct dc_context *ctx,
const struct dcn10_dwbc_registers *dwbc_regs,
const struct dcn10_dwbc_shift *dwbc_shift,
const struct dcn10_dwbc_mask *dwbc_mask,
int inst);
#endif
Annotation
- Detected declarations: `struct dcn10_dwbc_registers`, `struct dcn10_dwbc_mask`, `struct dcn10_dwbc_shift`, `struct dcn10_dwbc`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.