drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c- Extension
.c- Size
- 21811 bytes
- Lines
- 623
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dm_services.hcore_types.hresource.hcustom_float.hdcn10/dcn10_hwseq.hdce110/dce110_hwseq.hdce/dce_hwseq.habm.hdmcu.hdcn10/dcn10_optc.hdcn10/dcn10_dpp.hdcn10/dcn10_mpc.htiming_generator.hopp.hipp.hmpc.hreg_helper.hdcn10/dcn10_hubp.hdcn10/dcn10_hubbub.hdcn10_cm_common.hclk_mgr.h
Detected Declarations
function filesfunction dcn10_get_hubbub_statefunction dcn10_get_hubp_statesfunction dcn10_get_rq_statesfunction dcn10_get_dlg_statesfunction dcn10_get_ttu_statesfunction dcn10_get_cm_statesfunction dcn10_get_mpcc_statesfunction dcn10_get_otg_statesfunction dcn10_get_clock_statesfunction dcn10_clear_otpc_underflowfunction dcn10_clear_hubp_underflowfunction dcn10_clear_status_bitsfunction dcn10_get_hw_state
Annotated Snippet
if (!s->blank_en) {
if (invarOnly)
chars_printed = snprintf_count(pBuf, remaining_buffer, "%x,%x,%x,%d,%d,%x,%x,%x,%x,%x,%x,%x,"
"%d.%03d,%d.%03d,%d.%03d"
"\n",
hubp->inst,
s->pixel_format,
s->inuse_addr_hi,
s->viewport_width,
s->viewport_height,
s->rotation_angle,
s->h_mirror_en,
s->sw_mode,
s->dcc_en,
s->blank_en,
s->ttu_disable,
s->underflow_status,
(s->min_ttu_vblank * frac) / ref_clk_mhz / frac, (s->min_ttu_vblank * frac) / ref_clk_mhz % frac,
(s->qos_level_low_wm * frac) / ref_clk_mhz / frac, (s->qos_level_low_wm * frac) / ref_clk_mhz % frac,
(s->qos_level_high_wm * frac) / ref_clk_mhz / frac, (s->qos_level_high_wm * frac) / ref_clk_mhz % frac);
else
chars_printed = snprintf_count(pBuf, remaining_buffer, "%x,%x,%x,%x,%d,%d,%x,%x,%x,%x,%x,%x,%x,"
"%d.%03d,%d.%03d,%d.%03d"
"\n",
hubp->inst,
s->pixel_format,
s->inuse_addr_hi,
s->inuse_addr_lo,
s->viewport_width,
s->viewport_height,
s->rotation_angle,
s->h_mirror_en,
s->sw_mode,
s->dcc_en,
s->blank_en,
s->ttu_disable,
s->underflow_status,
(s->min_ttu_vblank * frac) / ref_clk_mhz / frac, (s->min_ttu_vblank * frac) / ref_clk_mhz % frac,
(s->qos_level_low_wm * frac) / ref_clk_mhz / frac, (s->qos_level_low_wm * frac) / ref_clk_mhz % frac,
(s->qos_level_high_wm * frac) / ref_clk_mhz / frac, (s->qos_level_high_wm * frac) / ref_clk_mhz % frac);
remaining_buffer -= chars_printed;
pBuf += chars_printed;
}
}
return bufSize - remaining_buffer;
}
static unsigned int dcn10_get_rq_states(struct dc *dc, char *pBuf, unsigned int bufSize)
{
struct resource_pool *pool = dc->res_pool;
unsigned int i;
unsigned int chars_printed = 0;
unsigned int remaining_buffer = bufSize;
chars_printed = snprintf_count(pBuf, remaining_buffer, "instance,drq_exp_m,prq_exp_m,mrq_exp_m,crq_exp_m,plane1_ba,"
"luma_chunk_s,luma_min_chu_s,luma_meta_ch_s,luma_min_m_c_s,luma_dpte_gr_s,luma_mpte_gr_s,luma_swath_hei,luma_pte_row_h,"
"chroma_chunk_s,chroma_min_chu_s,chroma_meta_ch_s,chroma_min_m_c_s,chroma_dpte_gr_s,chroma_mpte_gr_s,chroma_swath_hei,chroma_pte_row_h"
"\n");
remaining_buffer -= chars_printed;
pBuf += chars_printed;
for (i = 0; i < pool->pipe_count; i++) {
struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
if (!s->blank_en) {
chars_printed = snprintf_count(pBuf, remaining_buffer, "%x,%x,%x,%x,%x,%x,"
"%x,%x,%x,%x,%x,%x,%x,%x,"
"%x,%x,%x,%x,%x,%x,%x,%x"
"\n",
pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size,
rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
remaining_buffer -= chars_printed;
pBuf += chars_printed;
}
}
return bufSize - remaining_buffer;
}
Annotation
- Immediate include surface: `dm_services.h`, `core_types.h`, `resource.h`, `custom_float.h`, `dcn10/dcn10_hwseq.h`, `dce110/dce110_hwseq.h`, `dce/dce_hwseq.h`, `abm.h`.
- Detected declarations: `function files`, `function dcn10_get_hubbub_state`, `function dcn10_get_hubp_states`, `function dcn10_get_rq_states`, `function dcn10_get_dlg_states`, `function dcn10_get_ttu_states`, `function dcn10_get_cm_states`, `function dcn10_get_mpcc_states`, `function dcn10_get_otg_states`, `function dcn10_get_clock_states`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.