drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c- Extension
.c- Size
- 11142 bytes
- Lines
- 344
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
reg_helper.hresource.hdwb.hdcn20_dwb.h
Detected Declarations
enum dwb_outside_pix_strategyfunction dwb2_get_capsfunction dwb2_config_dwb_cnvfunction dwb2_enablefunction dwb2_disablefunction dwb2_updatefunction dwb2_is_enabledfunction dwb2_set_stereofunction dwb2_set_new_contentfunction dwb2_set_warmupfunction dwb2_set_scalerfunction dcn20_dwbc_construct
Annotated Snippet
if (params->cnv_params.crop_en) {
/* horizontal scale */
dwb_program_horz_scalar(dwbc20, params->cnv_params.crop_width,
params->dest_width,
params->scaler_taps);
/* vertical scale */
dwb_program_vert_scalar(dwbc20, params->cnv_params.crop_height,
params->dest_height,
params->scaler_taps,
params->subsample_position);
} else {
/* horizontal scale */
dwb_program_horz_scalar(dwbc20, params->cnv_params.src_width,
params->dest_width,
params->scaler_taps);
/* vertical scale */
dwb_program_vert_scalar(dwbc20, params->cnv_params.src_height,
params->dest_height,
params->scaler_taps,
params->subsample_position);
}
}
if (dwbc20->dwbc_mask->WBSCL_COEF_RAM_SEL) {
/* Swap double buffered coefficient set */
uint32_t wbscl_mode = REG_READ(WBSCL_MODE);
bool coef_ram_current = get_reg_field_value_ex(
wbscl_mode, dwbc20->dwbc_mask->WBSCL_COEF_RAM_SEL_CURRENT,
dwbc20->dwbc_shift->WBSCL_COEF_RAM_SEL_CURRENT);
REG_UPDATE(WBSCL_MODE, WBSCL_COEF_RAM_SEL, !coef_ram_current);
}
}
static const struct dwbc_funcs dcn20_dwbc_funcs = {
.get_caps = dwb2_get_caps,
.enable = dwb2_enable,
.disable = dwb2_disable,
.update = dwb2_update,
.is_enabled = dwb2_is_enabled,
.set_stereo = dwb2_set_stereo,
.set_new_content = dwb2_set_new_content,
.set_warmup = dwb2_set_warmup,
.dwb_set_scaler = dwb2_set_scaler,
};
void dcn20_dwbc_construct(struct dcn20_dwbc *dwbc20,
struct dc_context *ctx,
const struct dcn20_dwbc_registers *dwbc_regs,
const struct dcn20_dwbc_shift *dwbc_shift,
const struct dcn20_dwbc_mask *dwbc_mask,
int inst)
{
dwbc20->base.ctx = ctx;
dwbc20->base.inst = inst;
dwbc20->base.funcs = &dcn20_dwbc_funcs;
dwbc20->dwbc_regs = dwbc_regs;
dwbc20->dwbc_shift = dwbc_shift;
dwbc20->dwbc_mask = dwbc_mask;
}
Annotation
- Immediate include surface: `reg_helper.h`, `resource.h`, `dwb.h`, `dcn20_dwb.h`.
- Detected declarations: `enum dwb_outside_pix_strategy`, `function dwb2_get_caps`, `function dwb2_config_dwb_cnv`, `function dwb2_enable`, `function dwb2_disable`, `function dwb2_update`, `function dwb2_is_enabled`, `function dwb2_set_stereo`, `function dwb2_set_new_content`, `function dwb2_set_warmup`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.