drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
Extension
.h
Size
17273 bytes
Lines
432
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dcn20_dwbc_registers {
	/* DCN2.0 */
	uint32_t WB_ENABLE;
	uint32_t WB_EC_CONFIG;
	uint32_t CNV_MODE;
	uint32_t CNV_WINDOW_START;
	uint32_t CNV_WINDOW_SIZE;
	uint32_t CNV_UPDATE;
	uint32_t CNV_SOURCE_SIZE;
	uint32_t CNV_TEST_CNTL;
	uint32_t CNV_TEST_CRC_RED;
	uint32_t CNV_TEST_CRC_GREEN;
	uint32_t CNV_TEST_CRC_BLUE;
	uint32_t WB_DEBUG_CTRL;
	uint32_t WB_DBG_MODE;
	uint32_t WB_HW_DEBUG;
	uint32_t CNV_TEST_DEBUG_INDEX;
	uint32_t CNV_TEST_DEBUG_DATA;
	uint32_t WB_SOFT_RESET;
	uint32_t WBSCL_COEF_RAM_SELECT;
	uint32_t WBSCL_COEF_RAM_TAP_DATA;
	uint32_t WBSCL_MODE;
	uint32_t WBSCL_TAP_CONTROL;
	uint32_t WBSCL_DEST_SIZE;
	uint32_t WBSCL_HORZ_FILTER_SCALE_RATIO;
	uint32_t WBSCL_HORZ_FILTER_INIT_Y_RGB;
	uint32_t WBSCL_HORZ_FILTER_INIT_CBCR;
	uint32_t WBSCL_VERT_FILTER_SCALE_RATIO;
	uint32_t WBSCL_VERT_FILTER_INIT_Y_RGB;
	uint32_t WBSCL_VERT_FILTER_INIT_CBCR;
	uint32_t WBSCL_ROUND_OFFSET;
	uint32_t WBSCL_OVERFLOW_STATUS;
	uint32_t WBSCL_COEF_RAM_CONFLICT_STATUS;
	uint32_t WBSCL_TEST_CNTL;
	uint32_t WBSCL_TEST_CRC_RED;
	uint32_t WBSCL_TEST_CRC_GREEN;
	uint32_t WBSCL_TEST_CRC_BLUE;
	uint32_t WBSCL_BACKPRESSURE_CNT_EN;
	uint32_t WB_MCIF_BACKPRESSURE_CNT;
	uint32_t WBSCL_CLAMP_Y_RGB;
	uint32_t WBSCL_CLAMP_CBCR;
	uint32_t WBSCL_OUTSIDE_PIX_STRATEGY;
	uint32_t WBSCL_OUTSIDE_PIX_STRATEGY_CBCR;
	uint32_t WBSCL_DEBUG;
	uint32_t WBSCL_TEST_DEBUG_INDEX;
	uint32_t WBSCL_TEST_DEBUG_DATA;
	uint32_t WB_WARM_UP_MODE_CTL1;
	uint32_t WB_WARM_UP_MODE_CTL2;
};


struct dcn20_dwbc_mask {
	DWBC_REG_FIELD_LIST_DCN2_0(uint32_t)
};

struct dcn20_dwbc_shift {
	DWBC_REG_FIELD_LIST_DCN2_0(uint8_t)
};

struct dcn20_dwbc {
	struct dwbc base;
	const struct dcn20_dwbc_registers *dwbc_regs;
	const struct dcn20_dwbc_shift *dwbc_shift;
	const struct dcn20_dwbc_mask *dwbc_mask;
};

void dcn20_dwbc_construct(struct dcn20_dwbc *dwbc20,
	struct dc_context *ctx,
	const struct dcn20_dwbc_registers *dwbc_regs,
	const struct dcn20_dwbc_shift *dwbc_shift,
	const struct dcn20_dwbc_mask *dwbc_mask,
	int inst);

bool dwb2_disable(struct dwbc *dwbc);

bool dwb2_is_enabled(struct dwbc *dwbc);

void dwb2_set_stereo(struct dwbc *dwbc,
	struct dwb_stereo_params *stereo_params);

void dwb2_set_new_content(struct dwbc *dwbc,
	bool is_new_content);

void dwb2_config_dwb_cnv(struct dwbc *dwbc,
	struct dc_dwb_params *params);

void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params);

bool dwb_program_vert_scalar(struct dcn20_dwbc *dwbc20,
	uint32_t src_height,

Annotation

Implementation Notes