drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c
Extension
.c
Size
7350 bytes
Lines
212
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#include "reg_helper.h"

#include "core_types.h"
#include "link_encoder.h"
#include "dcn201_link_encoder.h"
#include "stream_encoder.h"
#include "dc_bios_types.h"

#include "gpio_service_interface.h"

#define CTX \
	enc10->base.ctx

#define DC_LOGGER \
	enc10->base.ctx->logger

#define REG(reg)\
	(enc10->link_regs->reg)

#undef FN
#define FN(reg_name, field_name) \
	enc10->link_shift->field_name, enc10->link_mask->field_name

#define IND_REG(index) \
	(enc10->link_regs->index)

static void dcn201_link_encoder_get_max_link_cap(struct link_encoder *enc,
						 struct dc_link_settings *link_settings)
{
	uint32_t value1, value2;
	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);

	dcn10_link_encoder_get_max_link_cap(enc, link_settings);
	REG_GET_2(RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DISABLE, &value1,
		 RDPCS_PHY_DPALT_DP4, &value2);
	/*limit to combo_phy*/
	if (enc->usbc_combo_phy) {
		if (!value1 && !value2 && link_settings->lane_count > LANE_COUNT_TWO)
			link_settings->lane_count = LANE_COUNT_TWO;
	}
}

static bool dcn201_link_encoder_is_in_alt_mode(struct link_encoder *enc)
{
	uint32_t value;
	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);

	REG_GET(RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DISABLE, &value);

	// if value == 1 alt mode is disabled, otherwise it is enabled
	return !value;
}

static const struct link_encoder_funcs dcn201_link_enc_funcs = {
	.read_state = link_enc2_read_state,
	.validate_output_with_stream =
		dcn10_link_encoder_validate_output_with_stream,
	.hw_init = enc2_hw_init,
	.setup = dcn10_link_encoder_setup,
	.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
	.enable_dp_output = dcn10_link_encoder_enable_dp_output,
	.enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
	.disable_output = dcn10_link_encoder_disable_output,
	.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
	.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
	.update_mst_stream_allocation_table =
		dcn10_link_encoder_update_mst_stream_allocation_table,
	.psr_program_dp_dphy_fast_training =
			dcn10_psr_program_dp_dphy_fast_training,
	.psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
	.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
	.enable_hpd = dcn10_link_encoder_enable_hpd,
	.disable_hpd = dcn10_link_encoder_disable_hpd,
	.is_dig_enabled = dcn10_is_dig_enabled,
	.destroy = dcn10_link_encoder_destroy,
	.fec_set_enable = enc2_fec_set_enable,
	.fec_set_ready = enc2_fec_set_ready,
	.get_dig_frontend = dcn10_get_dig_frontend,
	.fec_is_active = enc2_fec_is_active,
	.is_in_alt_mode = dcn201_link_encoder_is_in_alt_mode,
	.get_max_link_cap = dcn201_link_encoder_get_max_link_cap,
	.get_hpd_state = dcn10_get_hpd_state,
	.program_hpd_filter = dcn10_program_hpd_filter,
};

void dcn201_link_encoder_construct(
	struct dcn20_link_encoder *enc20,
	const struct encoder_init_data *init_data,
	const struct encoder_feature_support *enc_features,
	const struct dcn10_link_enc_registers *link_regs,

Annotation

Implementation Notes