drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.h- Extension
.h- Size
- 3730 bytes
- Lines
- 125
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct dcn31_apg_registersstruct dcn31_apg_shiftstruct dcn31_apg_maskstruct apgstruct apg_funcsstruct dcn31_apg
Annotated Snippet
struct dcn31_apg_registers {
uint32_t APG_CONTROL;
uint32_t APG_CONTROL2;
uint32_t APG_MEM_PWR;
uint32_t APG_DBG_GEN_CONTROL;
};
#define DCN31_APG_MASK_SH_LIST(mask_sh)\
SE_SF(APG0_APG_CONTROL, APG_RESET, mask_sh),\
SE_SF(APG0_APG_CONTROL, APG_RESET_DONE, mask_sh),\
SE_SF(APG0_APG_CONTROL2, APG_ENABLE, mask_sh),\
SE_SF(APG0_APG_CONTROL2, APG_DP_AUDIO_STREAM_ID, mask_sh),\
SE_SF(APG0_APG_DBG_GEN_CONTROL, APG_DBG_AUDIO_CHANNEL_ENABLE, mask_sh),\
SE_SF(APG0_APG_MEM_PWR, APG_MEM_PWR_FORCE, mask_sh)
#define APG_DCN31_REG_FIELD_LIST(type) \
type APG_RESET;\
type APG_RESET_DONE;\
type APG_ENABLE;\
type APG_DP_AUDIO_STREAM_ID;\
type APG_DBG_AUDIO_CHANNEL_ENABLE;\
type APG_MEM_PWR_FORCE
//APG0_APG_DBG_GEN_CONTROL
#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L
/* Not in DCN42B: APG_DBG_GEN_CONTROL, APG0_APG_DBG_60958 */
#define DCN42B_APG_MASK_SH_LIST(mask_sh)\
SE_SF(APG0_APG_CONTROL, APG_RESET, mask_sh),\
SE_SF(APG0_APG_CONTROL, APG_RESET_DONE, mask_sh),\
SE_SF(APG0_APG_CONTROL2, APG_ENABLE, mask_sh),\
SE_SF(APG0_APG_CONTROL2, APG_DP_AUDIO_STREAM_ID, mask_sh),\
SE_SF(APG0_APG_MEM_PWR, APG_MEM_PWR_FORCE, mask_sh),\
SE_SF(APG0_APG_DBG_GEN_CONTROL, APG_DBG_AUDIO_CHANNEL_ENABLE, mask_sh)
struct dcn31_apg_shift {
APG_DCN31_REG_FIELD_LIST(uint8_t);
};
struct dcn31_apg_mask {
APG_DCN31_REG_FIELD_LIST(uint32_t);
};
struct apg {
const struct apg_funcs *funcs;
struct dc_context *ctx;
int inst;
};
struct apg_funcs {
void (*setup_hdmi_audio)(
struct apg *apg);
void (*se_audio_setup)(
struct apg *apg,
unsigned int az_inst,
struct audio_info *audio_info);
void (*enable_apg)(
struct apg *apg);
void (*disable_apg)(
struct apg *apg);
};
struct dcn31_apg {
struct apg base;
const struct dcn31_apg_registers *regs;
const struct dcn31_apg_shift *apg_shift;
const struct dcn31_apg_mask *apg_mask;
};
void apg31_construct(struct dcn31_apg *apg3,
struct dc_context *ctx,
uint32_t inst,
const struct dcn31_apg_registers *apg_regs,
const struct dcn31_apg_shift *apg_shift,
const struct dcn31_apg_mask *apg_mask);
#endif
Annotation
- Detected declarations: `struct dcn31_apg_registers`, `struct dcn31_apg_shift`, `struct dcn31_apg_mask`, `struct apg`, `struct apg_funcs`, `struct dcn31_apg`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.