drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
Extension
.h
Size
22073 bytes
Lines
669
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dcn10_link_enc_aux_registers {
	uint32_t AUX_CONTROL;
	uint32_t AUX_DPHY_RX_CONTROL0;
	uint32_t AUX_DPHY_TX_CONTROL;
	uint32_t AUX_DPHY_RX_CONTROL1;
};

struct dcn10_link_enc_hpd_registers {
	uint32_t DC_HPD_CONTROL;
	uint32_t DC_HPD_INT_STATUS;
	uint32_t DC_HPD_TOGGLE_FILT_CNTL;
};

struct dcn10_link_enc_registers {
	uint32_t DIG_BE_CNTL;
	uint32_t DIG_BE_EN_CNTL;
	uint32_t DIG_CLOCK_PATTERN;
	uint32_t DP_CONFIG;
	uint32_t DP_DPHY_CNTL;
	uint32_t DP_DPHY_INTERNAL_CTRL;
	uint32_t DP_DPHY_PRBS_CNTL;
	uint32_t DP_DPHY_SCRAM_CNTL;
	uint32_t DP_DPHY_SYM0;
	uint32_t DP_DPHY_SYM1;
	uint32_t DP_DPHY_SYM2;
	uint32_t DP_DPHY_TRAINING_PATTERN_SEL;
	uint32_t DP_LINK_CNTL;
	uint32_t DP_LINK_FRAMING_CNTL;
	uint32_t DP_MSE_SAT0;
	uint32_t DP_MSE_SAT1;
	uint32_t DP_MSE_SAT2;
	uint32_t DP_MSE_SAT_UPDATE;
	uint32_t DP_SEC_CNTL;
	uint32_t DP_VID_STREAM_CNTL;
	uint32_t DP_DPHY_FAST_TRAINING;
	uint32_t DP_DPHY_BS_SR_SWAP_CNTL;
	uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
	uint32_t DP_SEC_CNTL1;
	uint32_t TMDS_CTL_BITS;
	/* DCCG  */
	uint32_t CLOCK_ENABLE;
	/* DIG */
	uint32_t DIG_LANE_ENABLE;
	/* UNIPHY */
	uint32_t CHANNEL_XBAR_CNTL;
	/* DPCS */
	uint32_t RDPCSTX_PHY_CNTL3;
	uint32_t RDPCSTX_PHY_CNTL4;
	uint32_t RDPCSTX_PHY_CNTL5;
	uint32_t RDPCSTX_PHY_CNTL6;
	uint32_t RDPCSPIPE_PHY_CNTL6;
	uint32_t RDPCSTX_PHY_CNTL7;
	uint32_t RDPCSTX_PHY_CNTL8;
	uint32_t RDPCSTX_PHY_CNTL9;
	uint32_t RDPCSTX_PHY_CNTL10;
	uint32_t RDPCSTX_PHY_CNTL11;
	uint32_t RDPCSTX_PHY_CNTL12;
	uint32_t RDPCSTX_PHY_CNTL13;
	uint32_t RDPCSTX_PHY_CNTL14;
	uint32_t RDPCSTX_PHY_CNTL15;
	uint32_t RDPCSTX_CNTL;
	uint32_t RDPCSTX_CLOCK_CNTL;
	uint32_t RDPCSTX_PHY_CNTL0;
	uint32_t RDPCSTX_PHY_CNTL2;
	uint32_t RDPCSTX_PLL_UPDATE_DATA;
	uint32_t RDPCS_TX_CR_ADDR;
	uint32_t RDPCS_TX_CR_DATA;
	uint32_t DPCSTX_TX_CLOCK_CNTL;
	uint32_t DPCSTX_TX_CNTL;
	uint32_t RDPCSTX_INTERRUPT_CONTROL;
	uint32_t RDPCSTX_PHY_FUSE0;
	uint32_t RDPCSTX_PHY_FUSE1;
	uint32_t RDPCSTX_PHY_FUSE2;
	uint32_t RDPCSTX_PHY_FUSE3;
	uint32_t RDPCSTX_PHY_RX_LD_VAL;
	uint32_t DPCSTX_DEBUG_CONFIG;
	uint32_t RDPCSTX_DEBUG_CONFIG;
	uint32_t RDPCSTX0_RDPCSTX_SCRATCH;
	uint32_t RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG;
	uint32_t DCIO_SOFT_RESET;
	/* indirect registers */
	uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2;
	uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3;
	uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2;
	uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3;
	uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2;
	uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3;
	uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2;
	uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3;
	uint32_t TMDS_DCBALANCER_CONTROL;

Annotation

Implementation Notes