drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c
Extension
.c
Size
16013 bytes
Lines
511
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#include "reg_helper.h"

#include "core_types.h"
#include "link_encoder.h"
#include "dcn30_dio_link_encoder.h"
#include "stream_encoder.h"
#include "dc_bios_types.h"
#include "gpio_service_interface.h"

#define CTX \
	enc10->base.ctx
#define DC_LOGGER \
	enc10->base.ctx->logger

#define REG(reg)\
	(enc10->link_regs->reg)

#undef FN
#define FN(reg_name, field_name) \
	enc10->link_shift->field_name, enc10->link_mask->field_name

#define IND_REG(index) \
	(enc10->link_regs->index)


static bool dcn30_link_encoder_validate_hdmi_frl_output(
	const struct dcn10_link_encoder *enc10,
	const struct dc_crtc_timing *crtc_timing)
{
	enum dc_color_depth max_deep_color =
			enc10->base.features.max_hdmi_deep_color;

	if (!enc10->base.features.flags.bits.IS_HDMI_FRL_CAPABLE)
		return false;

	if (max_deep_color < crtc_timing->display_color_depth)
		return false;

	if (crtc_timing->display_color_depth < COLOR_DEPTH_888)
		return false;

	/* TODO: check if hdmi_charclk is above ASIC cap (10 GBS for DCN3AG) */

	return true;
}

bool dcn30_link_encoder_validate_output_with_stream(
	struct link_encoder *enc,
	const struct dc_stream_state *stream)
{
	if (dc_is_hdmi_frl_signal(stream->signal)) {
		struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);

		return dcn30_link_encoder_validate_hdmi_frl_output(enc10, &stream->timing);
	} else {
		return dcn10_link_encoder_validate_output_with_stream(enc, stream);
	}
}

//---------------------------------------------------
// Task: Program EQ setting
// Note:
//      EQ setting can be dont during P2 state or P0 state
//      If set in P0 state, The values are latched in a single
//      cycle of txX_clk but will take maximum of 40 txX_clk symbols
//      to be reflected on the output. During this period the
//      analog serial lines might have a transitional behavior.
//---------------------------------------------------
void dpcs30_program_eq_setting(
		struct link_encoder *enc,
		uint8_t FFE_Level,
		bool de_emphasis_only,
		bool pre_shoot_only,
		bool no_ffe,
		const struct dc_hdmi_frl_link_settings *link_settings)
{
	(void)link_settings;
	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
	/* EQ setting for DP lane0 */
	uint32_t eq_main;
	uint32_t eq_pre;
	uint32_t eq_post;

	if (enc10->base.ctx->dc->debug.ignore_ffe)
		return;

	if (FFE_Level < 0x5)
		enc10->base.txffe_state = FFE_Level;

	if (FFE_Level == 0xEE) {

Annotation

Implementation Notes