drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h
Extension: .h
Size: 16712 bytes
Lines: 333
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

dcn30/dcn30_vpg.h
dcn30/dcn30_afmt.h
stream_encoder.h
dcn20/dcn20_stream_encoder.h

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef __DC_DIO_STREAM_ENCODER_DCN35_H__
#define __DC_DIO_STREAM_ENCODER_DCN35_H__

#include "dcn30/dcn30_vpg.h"
#include "dcn30/dcn30_afmt.h"
#include "stream_encoder.h"
#include "dcn20/dcn20_stream_encoder.h"

/* Register bit field name change */
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT                                        0x8
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT                                              0x9
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0xa
#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT                                                      0xe
#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT                                              0xf

#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK                                          0x00000100L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK                                                0x00000200L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000400L
#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK                                                        0x00004000L
#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK                                                0x00008000L


#define SE_DCN35_REG_LIST(id)\
	SRI(AFMT_CNTL, DIG, id), \
	SRI(DIG_FE_CNTL, DIG, id), \
	SRI(HDMI_CONTROL, DIG, id), \
	SRI(HDMI_DB_CONTROL, DIG, id), \
	SRI(HDMI_GC, DIG, id), \
	SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
	SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
	SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
	SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
	SRI(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \
	SRI(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \
	SRI(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \
	SRI(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \
	SRI(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \
	SRI(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \
	SRI(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \
	SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
	SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
	SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
	SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
	SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
	SRI(HDMI_ACR_32_0, DIG, id),\
	SRI(HDMI_ACR_32_1, DIG, id),\
	SRI(HDMI_ACR_44_0, DIG, id),\
	SRI(HDMI_ACR_44_1, DIG, id),\
	SRI(HDMI_ACR_48_0, DIG, id),\
	SRI(HDMI_ACR_48_1, DIG, id),\
	SRI(DP_DB_CNTL, DP, id), \
	SRI(DP_MSA_MISC, DP, id), \
	SRI(DP_MSA_VBID_MISC, DP, id), \
	SRI(DP_MSA_COLORIMETRY, DP, id), \
	SRI(DP_MSA_TIMING_PARAM1, DP, id), \
	SRI(DP_MSA_TIMING_PARAM2, DP, id), \
	SRI(DP_MSA_TIMING_PARAM3, DP, id), \
	SRI(DP_MSA_TIMING_PARAM4, DP, id), \
	SRI(DP_MSE_RATE_CNTL, DP, id), \
	SRI(DP_MSE_RATE_UPDATE, DP, id), \
	SRI(DP_PIXEL_FORMAT, DP, id), \
	SRI(DP_SEC_CNTL, DP, id), \
	SRI(DP_SEC_CNTL1, DP, id), \
	SRI(DP_SEC_CNTL2, DP, id), \
	SRI(DP_SEC_CNTL5, DP, id), \
	SRI(DP_SEC_CNTL6, DP, id), \
	SRI(DP_STEER_FIFO, DP, id), \
	SRI(DP_VID_M, DP, id), \
	SRI(DP_VID_N, DP, id), \
	SRI(DP_VID_STREAM_CNTL, DP, id), \
	SRI(DP_VID_TIMING, DP, id), \
	SRI(DP_SEC_AUD_N, DP, id), \
	SRI(DP_SEC_TIMESTAMP, DP, id), \
	SRI(DP_DSC_CNTL, DP, id), \
	SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
	SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
	SRI(DP_SEC_FRAMING4, DP, id), \
	SRI(DP_GSP11_CNTL, DP, id), \
	SRI(DME_CONTROL, DME, id),\
	SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
	SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
	SRI(DIG_FE_CNTL, DIG, id), \
	SRI(DIG_FE_EN_CNTL, DIG, id), \
	SRI(DIG_FE_CLK_CNTL, DIG, id), \
	SRI(DIG_CLOCK_PATTERN, DIG, id), \
	SRI(DIG_FIFO_CTRL0, DIG, id),\
	SRI(STREAM_MAPPER_CONTROL, DIG, id)


#define SE_COMMON_MASK_SH_LIST_DCN35(mask_sh)\

Annotation

Immediate include surface: `dcn30/dcn30_vpg.h`, `dcn30/dcn30_afmt.h`, `stream_encoder.h`, `dcn20/dcn20_stream_encoder.h`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.