drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c
Extension
.c
Size
7658 bytes
Lines
227
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: MIT
//
// Copyright 2026 Advanced Micro Devices, Inc.

#include "reg_helper.h"

#include "core_types.h"
#include "link_encoder.h"
#include "dcn35/dcn35_dio_link_encoder.h"
#include "dcn42_dio_link_encoder.h"

#ifndef MIN
#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
#endif

#define CTX \
	enc10->base.ctx
#define DC_LOGGER \
	enc10->base.ctx->logger

#define REG(reg)\
	(enc10->link_regs->reg)

#undef FN
#define FN(reg_name, field_name) \
	enc10->link_shift->field_name, enc10->link_mask->field_name

#define HPD_REG(reg)\
	(enc10->hpd_regs->reg)

#define HPD_REG_GET(reg_name, field, val)	\
		generic_reg_get(CTX, HPD_REG(reg_name), \
				FN(reg_name, field), val)

#define HPD_REG_SET_N(reg_name, n, initial_val, ...)	\
		generic_reg_set_ex(CTX, \
				HPD_REG(reg_name), \
				initial_val, \
				n, __VA_ARGS__)

#define HPD_REG_SET_2(reg, init_value, f1, v1, f2, v2)	\
		HPD_REG_SET_N(reg, 2, init_value, \
				FN(reg, f1), v1,\
				FN(reg, f2), v2)

bool dcn42_get_hpd_state(struct link_encoder *enc)
{
	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
	uint32_t state;

	HPD_REG_GET(DC_HPD_INT_STATUS, DC_HPD_SENSE, &state);

	return state;
}

bool dcn42_program_hpd_filter(struct link_encoder *enc, int delay_on_connect_in_ms,	int delay_on_disconnect_in_ms)
{
	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);

	HPD_REG_SET_2(DC_HPD_TOGGLE_FILT_CNTL, 0,
			DC_HPD_CONNECT_INT_DELAY, delay_on_connect_in_ms,
			DC_HPD_DISCONNECT_INT_DELAY, delay_on_disconnect_in_ms);

	return true;
}

static const struct link_encoder_funcs dcn42_link_enc_funcs = {
	.read_state = link_enc2_read_state,
	.validate_output_with_stream =
			dcn30_link_encoder_validate_output_with_stream,
	.hw_init = dcn35_link_encoder_init,
	.setup = dcn35_link_encoder_setup,
	.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
	.enable_dp_output = dcn35_link_encoder_enable_dp_output,
	.enable_dp_mst_output = dcn35_link_encoder_enable_dp_mst_output,
	.disable_output = dcn35_link_encoder_disable_output,
	.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
	.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
	.update_mst_stream_allocation_table =
		dcn10_link_encoder_update_mst_stream_allocation_table,
	.psr_program_dp_dphy_fast_training =
			dcn10_psr_program_dp_dphy_fast_training,
	.psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
	.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
	.enable_hpd = dcn10_link_encoder_enable_hpd,
	.disable_hpd = dcn10_link_encoder_disable_hpd,
	.is_dig_enabled = dcn35_is_dig_enabled,
	.destroy = dcn10_link_encoder_destroy,
	.fec_set_enable = enc2_fec_set_enable,
	.fec_set_ready = enc2_fec_set_ready,

Annotation

Implementation Notes