drivers/gpu/drm/amd/display/dc/dm_services_types.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dm_services_types.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dm_services_types.h
Extension
.h
Size
7507 bytes
Lines
276
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dm_pp_clock_range {
	int min_khz;
	int max_khz;
};

struct dm_pp_gpu_clock_range {
	struct dm_pp_clock_range sclk;
	struct dm_pp_clock_range mclk;
	struct dm_pp_clock_range eclk;
	struct dm_pp_clock_range dclk;
};

enum dm_pp_clock_type {
	DM_PP_CLOCK_TYPE_DISPLAY_CLK = 1,
	DM_PP_CLOCK_TYPE_ENGINE_CLK, /* System clock */
	DM_PP_CLOCK_TYPE_MEMORY_CLK,
	DM_PP_CLOCK_TYPE_DCFCLK,
	DM_PP_CLOCK_TYPE_DCEFCLK,
	DM_PP_CLOCK_TYPE_SOCCLK,
	DM_PP_CLOCK_TYPE_PIXELCLK,
	DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
	DM_PP_CLOCK_TYPE_DPPCLK,
	DM_PP_CLOCK_TYPE_FCLK,
};

#define DC_DECODE_PP_CLOCK_TYPE(clk_type) \
	(clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
	(clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
	(clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : \
	(clk_type) == DM_PP_CLOCK_TYPE_DCFCLK ? "DCF" : \
	(clk_type) == DM_PP_CLOCK_TYPE_DCEFCLK ? "DCEF" : \
	(clk_type) == DM_PP_CLOCK_TYPE_SOCCLK ? "SoC" : \
	(clk_type) == DM_PP_CLOCK_TYPE_PIXELCLK ? "Pixel" : \
	(clk_type) == DM_PP_CLOCK_TYPE_DISPLAYPHYCLK ? "Display PHY" : \
	(clk_type) == DM_PP_CLOCK_TYPE_DPPCLK ? "DPP" : \
	(clk_type) == DM_PP_CLOCK_TYPE_FCLK ? "F" : \
	"Invalid"

#define DM_PP_MAX_CLOCK_LEVELS 16

struct dm_pp_clock_levels {
	uint32_t num_levels;
	uint32_t clocks_in_khz[DM_PP_MAX_CLOCK_LEVELS];
};

struct dm_pp_clock_with_latency {
	uint32_t clocks_in_khz;
	uint32_t latency_in_us;
};

struct dm_pp_clock_levels_with_latency {
	uint32_t num_levels;
	struct dm_pp_clock_with_latency data[DM_PP_MAX_CLOCK_LEVELS];
};

struct dm_pp_clock_with_voltage {
	uint32_t clocks_in_khz;
	uint32_t voltage_in_mv;
};

struct dm_pp_clock_levels_with_voltage {
	uint32_t num_levels;
	struct dm_pp_clock_with_voltage data[DM_PP_MAX_CLOCK_LEVELS];
};

struct dm_pp_single_disp_config {
	enum signal_type signal;
	uint8_t transmitter;
	uint8_t ddi_channel_mapping;
	uint8_t pipe_idx;
	uint32_t src_height;
	uint32_t src_width;
	uint32_t v_refresh;
	uint32_t pixel_clock; /* Pixel clock in KHz (for HDMI only: normalized) */
	struct dc_link_settings link_settings; /* DP only */
};

#define MAX_WM_SETS 4

enum dm_pp_wm_set_id {
	WM_SET_A = 0,
	WM_SET_B,
	WM_SET_C,
	WM_SET_D,
	WM_SET_INVALID = 0xffff,
};

struct dm_pp_clock_range_for_wm_set {
	enum dm_pp_wm_set_id wm_set_id;
	uint32_t wm_min_eng_clk_in_khz;

Annotation

Implementation Notes