drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c- Extension
.c- Size
- 65800 bytes
- Lines
- 1623
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dm_services.hdc.hdcn_calcs.hdcn_calc_auto.hdal_asic_id.hresource.hresource/dcn10/dcn10_resource.hdcn10/dcn10_hubbub.hdml/dml1_display_rq_dlg_calc.hdcn_calc_math.h
Detected Declarations
function tl_sw_mode_to_bw_defsfunction tl_lb_bpp_to_intfunction tl_pixel_format_to_bw_defsfunction swizzle_mode_to_macro_tile_sizefunction pipe_ctx_to_e2e_pipe_paramsfunction dcn_bw_calc_rq_dlg_ttufunction split_stream_across_pipesfunction calc_wm_sets_and_perf_paramsfunction dcn_bw_apply_registry_overridefunction hack_disable_optional_pipe_splitfunction hack_force_pipe_splitfunction hack_bounding_boxfunction get_highest_allowed_voltage_levelfunction dcn_validate_bandwidthfunction dcn_bw_update_from_pplib_fclksfunction dcn_bw_update_from_pplib_dcfclksfunction dcn_get_soc_clksfunction dcn_bw_notify_pplib_of_wm_rangesfunction dcn_bw_sync_calcs_and_dml
Annotated Snippet
if (!pipe->plane_state) {
v->dcc_enable[input_idx] = dcn_bw_yes;
v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32;
v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s;
v->lb_bit_per_pixel[input_idx] = 30;
v->viewport_width[input_idx] = (float)pipe->stream->timing.h_addressable;
v->viewport_height[input_idx] = (float)pipe->stream->timing.v_addressable;
/*
* for cases where we have no plane, we want to validate up to 1080p
* source size because here we are only interested in if the output
* timing is supported or not. if we cannot support native resolution
* of the high res display, we still want to support lower res up scale
* to native
*/
if (v->viewport_width[input_idx] > 1920)
v->viewport_width[input_idx] = 1920;
if (v->viewport_height[input_idx] > 1080)
v->viewport_height[input_idx] = 1080;
v->scaler_rec_out_width[input_idx] = v->viewport_width[input_idx];
v->scaler_recout_height[input_idx] = v->viewport_height[input_idx];
v->override_hta_ps[input_idx] = 1.0f;
v->override_vta_ps[input_idx] = 1.0f;
v->override_hta_pschroma[input_idx] = 1.0f;
v->override_vta_pschroma[input_idx] = 1.0f;
v->source_scan[input_idx] = dcn_bw_hor;
} else {
v->viewport_height[input_idx] = (float)pipe->plane_res.scl_data.viewport.height;
v->viewport_width[input_idx] = (float)pipe->plane_res.scl_data.viewport.width;
v->scaler_rec_out_width[input_idx] = (float)pipe->plane_res.scl_data.recout.width;
v->scaler_recout_height[input_idx] = (float)pipe->plane_res.scl_data.recout.height;
if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) {
if (pipe->plane_state->rotation % 2 == 0) {
int viewport_end = pipe->plane_res.scl_data.viewport.width
+ pipe->plane_res.scl_data.viewport.x;
int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.width
+ pipe->bottom_pipe->plane_res.scl_data.viewport.x;
if (viewport_end > viewport_b_end)
v->viewport_width[input_idx] = (float)(viewport_end
- pipe->bottom_pipe->plane_res.scl_data.viewport.x);
else
v->viewport_width[input_idx] = (float)(viewport_b_end
- pipe->plane_res.scl_data.viewport.x);
} else {
int viewport_end = pipe->plane_res.scl_data.viewport.height
+ pipe->plane_res.scl_data.viewport.y;
int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.height
+ pipe->bottom_pipe->plane_res.scl_data.viewport.y;
if (viewport_end > viewport_b_end)
v->viewport_height[input_idx] = (float)(viewport_end
- pipe->bottom_pipe->plane_res.scl_data.viewport.y);
else
v->viewport_height[input_idx] = (float)(viewport_b_end
- pipe->plane_res.scl_data.viewport.y);
}
v->scaler_rec_out_width[input_idx] = (float)(pipe->plane_res.scl_data.recout.width
+ pipe->bottom_pipe->plane_res.scl_data.recout.width);
}
if (pipe->plane_state->rotation % 2 == 0) {
ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
|| v->scaler_rec_out_width[input_idx] == v->viewport_width[input_idx]);
ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
|| v->scaler_recout_height[input_idx] == v->viewport_height[input_idx]);
} else {
ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
|| v->scaler_recout_height[input_idx] == v->viewport_width[input_idx]);
ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
|| v->scaler_rec_out_width[input_idx] == v->viewport_height[input_idx]);
}
if (dc->debug.optimized_watermark) {
/*
* this method requires us to always re-calculate watermark when dcc change
* between flip.
*/
v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
} else {
/*
* allow us to disable dcc on the fly without re-calculating WM
*
* extra overhead for DCC is quite small. for 1080p WM without
* DCC is only 0.417fus lower (urgent goes from 6.979fus to 6.562fus)
*/
unsigned int bpe;
v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format(
pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no;
Annotation
- Immediate include surface: `dm_services.h`, `dc.h`, `dcn_calcs.h`, `dcn_calc_auto.h`, `dal_asic_id.h`, `resource.h`, `resource/dcn10/dcn10_resource.h`, `dcn10/dcn10_hubbub.h`.
- Detected declarations: `function tl_sw_mode_to_bw_defs`, `function tl_lb_bpp_to_int`, `function tl_pixel_format_to_bw_defs`, `function swizzle_mode_to_macro_tile_size`, `function pipe_ctx_to_e2e_pipe_params`, `function dcn_bw_calc_rq_dlg_ttu`, `function split_stream_across_pipes`, `function calc_wm_sets_and_perf_params`, `function dcn_bw_apply_registry_override`, `function hack_disable_optional_pipe_split`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.