drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
Extension
.c
Size
91360 bytes
Lines
2573
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
			if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
				pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
			else
				pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
		} else {
			pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
		}

		pipe_cnt++;
	}
}

void dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params,
				 struct dc_state *context,
				 display_e2e_pipe_params_st *pipes,
				 int pipe_cnt, int i)
{
	int k;

	dc_assert_fp_enabled();

	for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
		wb_arb_params->cli_watermark[k] = (unsigned int)(get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0);
		wb_arb_params->pstate_watermark[k] = (unsigned int)(get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000.0);
	}
	wb_arb_params->time_per_pixel = (unsigned int)(16.0 * 1000.0 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000)); /* 4 bit fraction, ms */
}

static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
{
	unsigned int i;
	for (i = 0; i < dc->res_pool->pipe_count; i++) {
		if (!context->res_ctx.pipe_ctx[i].stream)
			continue;
		if (dc_is_hdmi_frl_signal(context->res_ctx.pipe_ctx[i].stream->signal))
			return true;
		if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))
			return true;
	}
	return false;
}

static enum dcn_zstate_support_state  decide_zstate_support(struct dc *dc, struct dc_state *context)
{
	int plane_count;
	unsigned int i;

	plane_count = 0;
	for (i = 0; i < dc->res_pool->pipe_count; i++) {
		if (context->res_ctx.pipe_ctx[i].plane_state)
			plane_count++;
	}

	/*
	 * Z9 and Z10 allowed cases:
	 * 	1. 0 Planes enabled
	 * 	2. single eDP, on link 0, 1 plane and stutter period > 5ms
	 * Z10 only cases:
	 * 	1. single eDP, on link 0, 1 plane and stutter period >= 5ms
	 * Z8 cases:
	 * 	1. stutter period sufficient
	 * Zstate not allowed cases:
	 * 	1. Everything else
	 */
	if (plane_count == 0)
		return DCN_ZSTATE_SUPPORT_ALLOW;
	else if (context->stream_count == 1 &&  context->streams[0]->signal == SIGNAL_TYPE_EDP) {
		struct dc_link *link = context->streams[0]->sink->link;
		struct dc_stream_status *stream_status = &context->stream_status[0];
		int minmum_z8_residency = dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;
		bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;
		bool is_pwrseq0 = (link && link->link_index == 0);
		bool is_psr = (link && (link->psr_settings.psr_version == DC_PSR_VERSION_1 ||
						link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) && !link->panel_config.psr.disable_psr);
		bool is_replay = link && link->replay_settings.replay_feature_enabled;

		/* Don't support multi-plane configurations */
		if (stream_status->plane_count > 1)
			return DCN_ZSTATE_SUPPORT_DISALLOW;

		if (is_pwrseq0 && context->bw_ctx.dml.vba.StutterPeriod > 5000.0)
			return DCN_ZSTATE_SUPPORT_ALLOW;
		else if (is_pwrseq0 && (is_psr || is_replay))
			return DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY;
		else
			return allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY : DCN_ZSTATE_SUPPORT_DISALLOW;
	} else {
		return DCN_ZSTATE_SUPPORT_DISALLOW;
	}

Annotation

Implementation Notes