drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
Extension
.c
Size
147645 bytes
Lines
3601
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct pipe_slice_table {
	struct {
		struct dc_stream_state *stream;
		int slice_count;
	} odm_combines[MAX_STREAMS];
	int odm_combine_count;

	struct {
		struct pipe_ctx *pri_pipe;
		struct dc_plane_state *plane;
		int slice_count;
	} mpc_combines[MAX_PLANES];
	int mpc_combine_count;
};


static void update_slice_table_for_stream(struct pipe_slice_table *table,
		struct dc_stream_state *stream, int diff)
{
	int i;

	for (i = 0; i < table->odm_combine_count; i++) {
		if (table->odm_combines[i].stream == stream) {
			table->odm_combines[i].slice_count += diff;
			break;
		}
	}

	if (i == table->odm_combine_count) {
		table->odm_combine_count++;
		table->odm_combines[i].stream = stream;
		table->odm_combines[i].slice_count = diff;
	}
}

static void update_slice_table_for_plane(struct pipe_slice_table *table,
		struct pipe_ctx *dpp_pipe, struct dc_plane_state *plane, int diff)
{
	int i;
	struct pipe_ctx *pri_dpp_pipe = resource_get_primary_dpp_pipe(dpp_pipe);

	for (i = 0; i < table->mpc_combine_count; i++) {
		if (table->mpc_combines[i].plane == plane &&
				table->mpc_combines[i].pri_pipe == pri_dpp_pipe) {
			table->mpc_combines[i].slice_count += diff;
			break;
		}
	}

	if (i == table->mpc_combine_count) {
		table->mpc_combine_count++;
		table->mpc_combines[i].plane = plane;
		table->mpc_combines[i].pri_pipe = pri_dpp_pipe;
		table->mpc_combines[i].slice_count = diff;
	}
}

static void init_pipe_slice_table_from_context(
		struct pipe_slice_table *table,
		struct dc_state *context)
{
	int i, j;
	struct pipe_ctx *otg_master;
	struct pipe_ctx *dpp_pipes[MAX_PIPES];
	struct dc_stream_state *stream;
	int count;

	memset(table, 0, sizeof(*table));

	for (i = 0; i < context->stream_count; i++) {
		stream = context->streams[i];
		otg_master = resource_get_otg_master_for_stream(
				&context->res_ctx, stream);
		if (!otg_master)
			continue;

		count = resource_get_odm_slice_count(otg_master);
		update_slice_table_for_stream(table, stream, count);

		count = resource_get_dpp_pipes_for_opp_head(otg_master,
				&context->res_ctx, dpp_pipes);
		for (j = 0; j < count; j++)
			if (dpp_pipes[j]->plane_state)
				update_slice_table_for_plane(table, dpp_pipes[j],
						dpp_pipes[j]->plane_state, 1);
	}
}

static bool update_pipe_slice_table_with_split_flags(
		struct pipe_slice_table *table,

Annotation

Implementation Notes