drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
Extension
.c
Size
31043 bytes
Lines
615
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (is_phantom_pipe) {
			detile_buf_plane1_addr = (unsigned int)((1024.0 * 1024.0) / 2.0 / 1024.0); // half to chroma
		} else {
			if (stored_swath_l_bytes / stored_swath_c_bytes <= 1.5) {
				detile_buf_plane1_addr = (unsigned int)(detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma
#ifdef __DML_RQ_DLG_CALC_DEBUG__
				dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d (1/2 to chroma)\n",
						__func__, detile_buf_plane1_addr);
#endif
			} else {
				detile_buf_plane1_addr = (unsigned int)(
						dml_round_to_multiple(
								(unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0),
								1024, 0) / 1024.0); // 2/3 to luma
#ifdef __DML_RQ_DLG_CALC_DEBUG__
				dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d (1/3 chroma)\n",
						__func__, detile_buf_plane1_addr);
#endif
			}
		}
	}
	rq_regs->plane1_base_address = detile_buf_plane1_addr;

#ifdef __DML_RQ_DLG_CALC_DEBUG__
	dml_print("DML_DLG: %s: is_phantom_pipe = %d\n", __func__, is_phantom_pipe);
	dml_print("DML_DLG: %s: stored_swath_l_bytes = %f\n", __func__, stored_swath_l_bytes);
	dml_print("DML_DLG: %s: stored_swath_c_bytes = %f\n", __func__, stored_swath_c_bytes);
	dml_print("DML_DLG: %s: detile_buf_size_in_bytes = %d\n", __func__, detile_buf_size_in_bytes);
	dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d\n", __func__, detile_buf_plane1_addr);
	dml_print("DML_DLG: %s: plane1_base_address = %d\n", __func__, rq_regs->plane1_base_address);
#endif
	print__rq_regs_st(mode_lib, rq_regs);
	dml_print("DML_DLG::%s: Calculation for pipe[%d] done, num_pipes=%d\n", __func__, pipe_idx, num_pipes);
}

void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
		display_dlg_regs_st *dlg_regs,
		display_ttu_regs_st *ttu_regs,
		display_e2e_pipe_params_st *e2e_pipe_param,
		const unsigned int num_pipes,
		const unsigned int pipe_idx)
{
	const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
	const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
	const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
	double refcyc_per_req_delivery_pre_cur0 = 0.;
	double refcyc_per_req_delivery_cur0 = 0.;
	double refcyc_per_req_delivery_pre_c = 0.;
	double refcyc_per_req_delivery_c = 0.;
	double refcyc_per_req_delivery_pre_l;
	double refcyc_per_req_delivery_l;
	double refcyc_per_line_delivery_pre_c = 0.;
	double refcyc_per_line_delivery_c = 0.;
	double refcyc_per_line_delivery_pre_l;
	double refcyc_per_line_delivery_l;
	double min_ttu_vblank;
	double vratio_pre_l;
	double vratio_pre_c;
	unsigned int min_dst_y_next_start;
	unsigned int htotal = dst->htotal;
	unsigned int hblank_end = dst->hblank_end;
	unsigned int vblank_end = dst->vblank_end;
	bool interlaced = dst->interlaced;
	double pclk_freq_in_mhz = dst->pixel_rate_mhz;
	unsigned int vready_after_vcount0;
	double refclk_freq_in_mhz = clks->refclk_mhz;
	double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
	bool dual_plane = 0;
	unsigned int pipe_index_in_combine[DC__NUM_PIPES__MAX];
	unsigned int dst_x_after_scaler;
	unsigned int dst_y_after_scaler;
	double dst_y_prefetch;
	double dst_y_per_vm_vblank;
	double dst_y_per_row_vblank;
	double dst_y_per_vm_flip;
	double dst_y_per_row_flip;
	double max_dst_y_per_vm_vblank = 32.0;
	double max_dst_y_per_row_vblank = 16.0;
	double dst_y_per_pte_row_nom_l;
	double dst_y_per_pte_row_nom_c;
	double dst_y_per_meta_row_nom_l;
	double dst_y_per_meta_row_nom_c;
	double refcyc_per_pte_group_nom_l;
	double refcyc_per_pte_group_nom_c;
	double refcyc_per_pte_group_vblank_l;
	double refcyc_per_pte_group_vblank_c;
	double refcyc_per_pte_group_flip_l;
	double refcyc_per_pte_group_flip_c;
	double refcyc_per_meta_chunk_nom_l;
	double refcyc_per_meta_chunk_nom_c;

Annotation

Implementation Notes