drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.h
Extension
.h
Size
2814 bytes
Lines
71
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __DML32_DISPLAY_RQ_DLG_CALC_H__
#define __DML32_DISPLAY_RQ_DLG_CALC_H__

#include "../display_rq_dlg_helpers.h"

struct display_mode_lib;

/*
* Function: dml_rq_dlg_get_rq_reg
*  Main entry point for test to get the register values out of this DML class.
*  This function calls <get_rq_param> and <extract_rq_regs> functions to calculate
*  and then populate the rq_regs struct
* Input:
*  pipe_param - pipe source configuration (e.g. vp, pitch, scaling, dest, etc.)
* Output:
*  rq_regs - struct that holds all the RQ registers field value.
*            See also: <display_rq_regs_st>
*/
void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs,
		struct display_mode_lib *mode_lib,
		const display_e2e_pipe_params_st *e2e_pipe_param,
		const unsigned int num_pipes,
		const unsigned int pipe_idx);

/*
* Function: dml_rq_dlg_get_dlg_reg
*   Calculate and return DLG and TTU register struct given the system setting
* Output:
*  dlg_regs - output DLG register struct
*  ttu_regs - output DLG TTU register struct
* Input:
*  e2e_pipe_param - "compacted" array of e2e pipe param struct
*  num_pipes - num of active "pipe" or "route"
*  pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
*  cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
*           Added for legacy or unrealistic timing tests.
*/
void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
		display_dlg_regs_st *dlg_regs,
		display_ttu_regs_st *ttu_regs,
		display_e2e_pipe_params_st *e2e_pipe_param,
		const unsigned int num_pipes,
		const unsigned int pipe_idx);

#endif

Annotation

Implementation Notes