drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
Extension
.c
Size
21815 bytes
Lines
636
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (clk_table->num_entries == 1) {
			/*smu gives one DPM level, let's take the highest one*/
			closest_clk_lvl = dcn3_51_soc.num_states - 1;
		}

		clock_limits[i].state = i;

		/* Clocks dependent on voltage level. */
		clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
		if (clk_table->num_entries == 1 &&
			clock_limits[i].dcfclk_mhz <
			dcn3_51_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
			/*SMU fix not released yet*/
			clock_limits[i].dcfclk_mhz =
				dcn3_51_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
		}

		clock_limits[i].fabricclk_mhz =
			clk_table->entries[i].fclk_mhz;
		clock_limits[i].socclk_mhz =
			clk_table->entries[i].socclk_mhz;

		if (clk_table->entries[i].memclk_mhz &&
			clk_table->entries[i].wck_ratio)
			clock_limits[i].dram_speed_mts =
				clk_table->entries[i].memclk_mhz * 2 *
				clk_table->entries[i].wck_ratio;

		/* Clocks independent of voltage level. */
		clock_limits[i].dispclk_mhz = max_dispclk_mhz ?
			max_dispclk_mhz :
			dcn3_51_soc.clock_limits[closest_clk_lvl].dispclk_mhz;

		clock_limits[i].dppclk_mhz = max_dppclk_mhz ?
			max_dppclk_mhz :
			dcn3_51_soc.clock_limits[closest_clk_lvl].dppclk_mhz;

		clock_limits[i].dram_bw_per_chan_gbps =
			dcn3_51_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
		clock_limits[i].dscclk_mhz =
			dcn3_51_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
		clock_limits[i].dtbclk_mhz =
			dcn3_51_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
		clock_limits[i].phyclk_d18_mhz =
			dcn3_51_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
		clock_limits[i].phyclk_mhz =
			dcn3_51_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
	}

	memcpy(dcn3_51_soc.clock_limits, clock_limits,
		sizeof(dcn3_51_soc.clock_limits));

	if (clk_table->num_entries)
		dcn3_51_soc.num_states = clk_table->num_entries;

	if (max_dispclk_mhz) {
		dcn3_51_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
		dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
	}
	if ((int)(dcn3_51_soc.dram_clock_change_latency_us * 1000)
				!= dc->debug.dram_clock_change_latency_ns
			&& dc->debug.dram_clock_change_latency_ns) {
		dcn3_51_soc.dram_clock_change_latency_us =
			dc->debug.dram_clock_change_latency_ns / 1000.0;
	}

	if (dc->bb_overrides.dram_clock_change_latency_ns > 0)
		dcn3_51_soc.dram_clock_change_latency_us =
			dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;

	if (dc->bb_overrides.sr_exit_time_ns > 0)
		dcn3_51_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;

	if (dc->bb_overrides.sr_enter_plus_exit_time_ns > 0)
		dcn3_51_soc.sr_enter_plus_exit_time_us =
			dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;

	if (dc->bb_overrides.sr_exit_z8_time_ns > 0)
		dcn3_51_soc.sr_exit_z8_time_us = dc->bb_overrides.sr_exit_z8_time_ns / 1000.0;

	if (dc->bb_overrides.sr_enter_plus_exit_z8_time_ns > 0)
		dcn3_51_soc.sr_enter_plus_exit_z8_time_us =
			dc->bb_overrides.sr_enter_plus_exit_z8_time_ns / 1000.0;

	/*temp till dml2 fully work without dml1*/
	dml_init_instance(&dc->dml, &dcn3_51_soc, &dcn3_51_ip,
			  DML_PROJECT_DCN31);

	/*copy to dml2, before dml2_create*/
	if (clk_table->num_entries > 2) {

Annotation

Implementation Notes