drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h

Extension

.h

Size

537 bytes

Lines

20

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• clk_mgr.h

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef __DCN351_FPU_H__
#define __DCN351_FPU_H__

#include "clk_mgr.h"

void dcn351_update_bw_bounding_box_fpu(struct dc *dc,
				      struct clk_bw_params *bw_params);

int dcn351_populate_dml_pipes_from_context_fpu(struct dc *dc,
					      struct dc_state *context,
					      display_e2e_pipe_params_st *pipes,
					      enum dc_validate_mode validate_mode);

void dcn351_decide_zstate_support(struct dc *dc, struct dc_state *context);

#endif

Annotation

• Immediate include surface: `clk_mgr.h`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.