drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c- Extension
.c- Size
- 553318 bytes
- Lines
- 10455
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
display_mode_core.hdisplay_mode_util.hdisplay_mode_lib_defines.hdml_frl_cap_chk.hlib_frl_cap_check.hdml_assert.h
Detected Declarations
function dscceComputeDelayfunction dscComputeDelayfunction CalculatePrefetchSchedulefunction CalculateBytePerPixelAndBlockSizesfunction CalculateTWaitfunction CalculatePrefetchModefunction CalculateWriteBackDISPCLKfunction CalculateWriteBackDelayfunction CalculateVUpdateAndDynamicMetadataParametersfunction CalculateRowBandwidthfunction CalculateFlipSchedulefunction RoundToDFSGranularityfunction CalculateDCCConfigurationfunction CalculatePrefetchSourceLinesfunction CalculateVMAndRowBytesfunction PixelClockAdjustmentForProgressiveToInterlaceUnitfunction TruncToValidBPPfunction CalculateWatermarksMALLUseAndDRAMSpeedChangeSupportfunction CalculateDCFCLKDeepSleepfunction CalculateUrgentBurstFactorfunction CalculatePixelDeliveryTimesfunction CalculateMetaAndPTETimesfunction CalculateVMGroupAndRequestTimesfunction CalculateStutterEfficiencyfunction CalculateSwathAndDETConfigurationfunction CalculateExtraLatencyfunction CalculateHostVMDynamicLevelsfunction CalculateExtraLatencyBytesfunction CalculateUrgentLatencyfunction RequiredDTBCLKfunction UseMinimumDCFCLKfunction UnboundedRequestfunction CalculateSurfaceSizeInMallfunction CalculateDETBufferSizefunction CalculateMaxDETAndMinCompressedBufferSizefunction CalculateVMRowAndSwathfunction CalculateOutputLinkfunction CalculateODMModefunction CalculateRequiredDispclkfunction CalculateSinglePipeDPPCLKAndSCLThroughputfunction CalculateDPPCLKfunction CalculateMALLUseForStaticScreenfunction dml_get_return_bw_mbps_vm_onlyfunction dml_get_return_bw_mbpsfunction dml_get_return_dram_bw_mbpsfunction DSCDelayRequirementfunction CalculateVActiveBandwithSupportfunction CalculatePrefetchBandwithSupport
Annotated Snippet
if (p->VStartup * s->LineTime < *p->TSetup + *p->Tdmdl + s->Tdmbf + s->Tdmec + s->Tdmsks) {
*p->NotEnoughTimeForDynamicMetadata = true;
dml_print("DML::%s: Not Enough Time for Dynamic Meta!\n", __func__);
dml_print("DML::%s: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", __func__, s->Tdmbf);
dml_print("DML::%s: Tdmec: %fus - time dio takes to transfer dmd\n", __func__, s->Tdmec);
dml_print("DML::%s: Tdmsks: %fus - time before active dmd must complete transmission at dio\n", __func__, s->Tdmsks);
dml_print("DML::%s: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", __func__, *p->Tdmdl);
} else {
*p->NotEnoughTimeForDynamicMetadata = false;
}
} else {
*p->NotEnoughTimeForDynamicMetadata = false;
}
*p->Tdmdl_vm = (p->DynamicMetadataEnable == true && p->DynamicMetadataVMEnabled == true && p->GPUVMEnable == true ? p->TWait + s->Tvm_trips : 0);
if (p->myPipe->ScalerEnabled)
s->DPPCycles = (dml_uint_t)(p->DPPCLKDelaySubtotalPlusCNVCFormater + p->DPPCLKDelaySCL);
else
s->DPPCycles = (dml_uint_t)(p->DPPCLKDelaySubtotalPlusCNVCFormater + p->DPPCLKDelaySCLLBOnly);
s->DPPCycles = (dml_uint_t)(s->DPPCycles + p->myPipe->NumberOfCursors * p->DPPCLKDelayCNVCCursor);
s->DISPCLKCycles = (dml_uint_t)p->DISPCLKDelaySubtotal;
if (p->myPipe->Dppclk == 0.0 || p->myPipe->Dispclk == 0.0)
return true;
*p->DSTXAfterScaler = (dml_uint_t) dml_round(s->DPPCycles * p->myPipe->PixelClock / p->myPipe->Dppclk + s->DISPCLKCycles * p->myPipe->PixelClock / p->myPipe->Dispclk + p->DSCDelay, true);
*p->DSTXAfterScaler = (dml_uint_t) dml_round(*p->DSTXAfterScaler + (p->myPipe->ODMMode != dml_odm_mode_bypass ? 18 : 0) + (p->myPipe->DPPPerSurface - 1) * p->DPP_RECOUT_WIDTH +
((p->myPipe->ODMMode == dml_odm_mode_split_1to2 || p->myPipe->ODMMode == dml_odm_mode_mso_1to2) ? (dml_float_t)p->myPipe->HActive / 2.0 : 0) +
((p->myPipe->ODMMode == dml_odm_mode_mso_1to4) ? (dml_float_t)p->myPipe->HActive * 3.0 / 4.0 : 0), true);
#ifdef __DML_VBA_DEBUG__
dml_print("DML::%s: DPPCycles = %u\n", __func__, s->DPPCycles);
dml_print("DML::%s: PixelClock = %f\n", __func__, p->myPipe->PixelClock);
dml_print("DML::%s: Dppclk = %f\n", __func__, p->myPipe->Dppclk);
dml_print("DML::%s: DISPCLKCycles = %u\n", __func__, s->DISPCLKCycles);
dml_print("DML::%s: DISPCLK = %f\n", __func__, p->myPipe->Dispclk);
dml_print("DML::%s: DSCDelay = %u\n", __func__, p->DSCDelay);
dml_print("DML::%s: ODMMode = %u\n", __func__, p->myPipe->ODMMode);
dml_print("DML::%s: DPP_RECOUT_WIDTH = %u\n", __func__, p->DPP_RECOUT_WIDTH);
dml_print("DML::%s: DSTXAfterScaler = %u\n", __func__, *p->DSTXAfterScaler);
#endif
if (p->OutputFormat == dml_420 || (p->myPipe->InterlaceEnable && p->myPipe->ProgressiveToInterlaceUnitInOPP))
*p->DSTYAfterScaler = 1;
else
*p->DSTYAfterScaler = 0;
s->DSTTotalPixelsAfterScaler = *p->DSTYAfterScaler * p->myPipe->HTotal + *p->DSTXAfterScaler;
*p->DSTYAfterScaler = (dml_uint_t)(dml_floor(s->DSTTotalPixelsAfterScaler / p->myPipe->HTotal, 1));
*p->DSTXAfterScaler = (dml_uint_t)(s->DSTTotalPixelsAfterScaler - ((dml_float_t) (*p->DSTYAfterScaler * p->myPipe->HTotal)));
#ifdef __DML_VBA_DEBUG__
dml_print("DML::%s: DSTXAfterScaler = %u (final)\n", __func__, *p->DSTXAfterScaler);
dml_print("DML::%s: DSTYAfterScaler = %u (final)\n", __func__, *p->DSTYAfterScaler);
#endif
s->MyError = false;
s->Tr0_trips = s->trip_to_mem * (s->HostVMDynamicLevelsTrips + 1);
if (p->GPUVMEnable == true) {
s->Tvm_trips_rounded = dml_ceil(4.0 * s->Tvm_trips / s->LineTime, 1.0) / 4.0 * s->LineTime;
s->Tr0_trips_rounded = dml_ceil(4.0 * s->Tr0_trips / s->LineTime, 1.0) / 4.0 * s->LineTime;
if (p->GPUVMPageTableLevels >= 3) {
*p->Tno_bw = p->UrgentExtraLatency + s->trip_to_mem * (dml_float_t) ((p->GPUVMPageTableLevels - 2) * (s->HostVMDynamicLevelsTrips + 1) - 1);
} else if (p->GPUVMPageTableLevels == 1 && p->myPipe->DCCEnable != true) {
s->Tr0_trips_rounded = dml_ceil(4.0 * p->UrgentExtraLatency / s->LineTime, 1.0) / 4.0 * s->LineTime;
*p->Tno_bw = p->UrgentExtraLatency;
} else {
*p->Tno_bw = 0;
}
} else if (p->myPipe->DCCEnable == true) {
s->Tvm_trips_rounded = s->LineTime / 4.0;
s->Tr0_trips_rounded = dml_ceil(4.0 * s->Tr0_trips / s->LineTime, 1.0) / 4.0 * s->LineTime;
*p->Tno_bw = 0;
} else {
s->Tvm_trips_rounded = s->LineTime / 4.0;
s->Tr0_trips_rounded = s->LineTime / 2.0;
*p->Tno_bw = 0;
}
s->Tvm_trips_rounded = dml_max(s->Tvm_trips_rounded, s->LineTime / 4.0);
s->Tr0_trips_rounded = dml_max(s->Tr0_trips_rounded, s->LineTime / 4.0);
if (p->myPipe->SourcePixelFormat == dml_420_8 || p->myPipe->SourcePixelFormat == dml_420_10 || p->myPipe->SourcePixelFormat == dml_420_12) {
s->bytes_pp = p->myPipe->BytePerPixelY + p->myPipe->BytePerPixelC / 4;
} else {
s->bytes_pp = p->myPipe->BytePerPixelY + p->myPipe->BytePerPixelC;
}
Annotation
- Immediate include surface: `display_mode_core.h`, `display_mode_util.h`, `display_mode_lib_defines.h`, `dml_frl_cap_chk.h`, `lib_frl_cap_check.h`, `dml_assert.h`.
- Detected declarations: `function dscceComputeDelay`, `function dscComputeDelay`, `function CalculatePrefetchSchedule`, `function CalculateBytePerPixelAndBlockSizes`, `function CalculateTWait`, `function CalculatePrefetchMode`, `function CalculateWriteBackDISPCLK`, `function CalculateWriteBackDelay`, `function CalculateVUpdateAndDynamicMetadataParameters`, `function CalculateRowBandwidth`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.