drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core_structs.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core_structs.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core_structs.h
Extension: .h
Size: 81371 bytes
Lines: 2033
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

display_mode_lib_defines.h
dml_top_display_cfg_types.h

Detected Declarations

struct soc_state_bounding_box_st
struct soc_bounding_box_st
struct ip_params_st
struct DmlPipe
struct Watermarks
struct SOCParametersList
struct dml_plane_cfg_st
struct dml_surface_cfg_st
struct dml_timing_cfg_st
struct dml_output_cfg_st
struct dml_writeback_cfg_st
struct dml_hw_resource_st
struct dml_clk_cfg_st
struct dml_display_cfg_st
struct dml_mode_eval_policy_st
struct dml_mode_support_info_st
struct mode_support_st
struct mode_program_st
struct soc_states_st
struct UseMinimumDCFCLK_params_st
struct CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params_st
struct CalculateVMRowAndSwath_params_st
struct CalculateSwathAndDETConfiguration_params_st
struct CalculateStutterEfficiency_params_st
struct CalculatePrefetchSchedule_params_st
struct dml_core_mode_support_locals_st
struct dml_core_mode_programming_locals_st
struct CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals_st
struct CalculateVMRowAndSwath_locals_st
struct UseMinimumDCFCLK_locals_st
struct CalculatePrefetchSchedule_locals_st
struct display_mode_lib_scratch_st
struct display_mode_lib_st
struct dml_mode_support_ex_params_st
struct _vcs_dpi_dml_display_dlg_regs_st
struct _vcs_dpi_dml_display_ttu_regs_st
struct _vcs_dpi_dml_display_arb_params_st
struct _vcs_dpi_dml_display_plane_rq_regs_st
struct _vcs_dpi_dml_display_rq_regs_st
enum dml_project_id
enum dml_prefetch_modes
enum dml_use_mall_for_pstate_change_mode
enum dml_use_mall_for_static_screen_mode
enum dml_output_encoder_class
enum dml_output_link_dp_rate
enum dml_output_type_and_rate__type
enum dml_output_type_and_rate__rate
enum dml_output_format_class

Annotated Snippet

struct soc_state_bounding_box_st {
	dml_float_t socclk_mhz;
	dml_float_t dscclk_mhz;
	dml_float_t phyclk_mhz;
	dml_float_t phyclk_d18_mhz;
	dml_float_t phyclk_d32_mhz;
	dml_float_t dtbclk_mhz;
	dml_float_t fabricclk_mhz;
	dml_float_t dcfclk_mhz;
	dml_float_t dispclk_mhz;
	dml_float_t dppclk_mhz;
	dml_float_t dram_speed_mts;
	dml_float_t urgent_latency_pixel_data_only_us;
	dml_float_t urgent_latency_pixel_mixed_with_vm_data_us;
	dml_float_t urgent_latency_vm_data_only_us;
	dml_float_t writeback_latency_us;
	dml_float_t urgent_latency_adjustment_fabric_clock_component_us;
	dml_float_t urgent_latency_adjustment_fabric_clock_reference_mhz;
	dml_float_t sr_exit_time_us;
	dml_float_t sr_enter_plus_exit_time_us;
	dml_float_t sr_exit_z8_time_us;
	dml_float_t sr_enter_plus_exit_z8_time_us;
	dml_float_t dram_clock_change_latency_us;
	dml_float_t fclk_change_latency_us;
	dml_float_t usr_retraining_latency_us;
	dml_bool_t use_ideal_dram_bw_strobe;
	dml_float_t g6_temp_read_blackout_us;

	struct {
		dml_uint_t urgent_ramp_uclk_cycles;
		dml_uint_t trip_to_memory_uclk_cycles;
		dml_uint_t meta_trip_to_memory_uclk_cycles;
		dml_uint_t maximum_latency_when_urgent_uclk_cycles;
		dml_uint_t average_latency_when_urgent_uclk_cycles;
		dml_uint_t maximum_latency_when_non_urgent_uclk_cycles;
		dml_uint_t average_latency_when_non_urgent_uclk_cycles;
	}  dml_dcn401_uclk_dpm_dependent_soc_qos_params;
};

struct soc_bounding_box_st {
	dml_float_t dprefclk_mhz;
	dml_float_t xtalclk_mhz;
	dml_float_t pcierefclk_mhz;
	dml_float_t refclk_mhz;
	dml_float_t amclk_mhz;
	dml_uint_t max_outstanding_reqs;
	dml_float_t pct_ideal_sdp_bw_after_urgent;
	dml_float_t pct_ideal_fabric_bw_after_urgent;
	dml_float_t pct_ideal_dram_bw_after_urgent_pixel_only;
	dml_float_t pct_ideal_dram_bw_after_urgent_pixel_and_vm;
	dml_float_t pct_ideal_dram_bw_after_urgent_vm_only;
	dml_float_t pct_ideal_dram_bw_after_urgent_strobe;
	dml_float_t max_avg_sdp_bw_use_normal_percent;
	dml_float_t max_avg_fabric_bw_use_normal_percent;
	dml_float_t max_avg_dram_bw_use_normal_percent;
	dml_float_t max_avg_dram_bw_use_normal_strobe_percent;

	dml_float_t svp_prefetch_pct_ideal_sdp_bw_after_urgent;
	dml_float_t svp_prefetch_pct_ideal_fabric_bw_after_urgent;
	dml_float_t svp_prefetch_pct_ideal_dram_bw_after_urgent_pixel_only;
	dml_float_t svp_prefetch_pct_ideal_dram_bw_after_urgent_pixel_and_vm;
	dml_float_t svp_prefetch_pct_ideal_dram_bw_after_urgent_vm_only;
	dml_float_t svp_prefetch_max_avg_sdp_bw_use_normal_percent;
	dml_float_t svp_prefetch_max_avg_fabric_bw_use_normal_percent;
	dml_float_t svp_prefetch_max_avg_dram_bw_use_normal_percent;

	dml_uint_t round_trip_ping_latency_dcfclk_cycles;
	dml_uint_t urgent_out_of_order_return_per_channel_pixel_only_bytes;
	dml_uint_t urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
	dml_uint_t urgent_out_of_order_return_per_channel_vm_only_bytes;
	dml_uint_t num_chans;
	dml_uint_t return_bus_width_bytes;
	dml_uint_t dram_channel_width_bytes;
	dml_uint_t fabric_datapath_to_dcn_data_return_bytes;
	dml_uint_t hostvm_min_page_size_kbytes;
	dml_uint_t gpuvm_min_page_size_kbytes;
	dml_float_t phy_downspread_percent;
	dml_float_t dcn_downspread_percent;
	dml_float_t smn_latency_us;
	dml_uint_t mall_allocated_for_dcn_mbytes;
	dml_float_t dispclk_dppclk_vco_speed_mhz;
	dml_bool_t do_urgent_latency_adjustment;

	dml_uint_t mem_word_bytes;
	dml_uint_t num_dcc_mcaches;
	dml_uint_t mcache_size_bytes;
	dml_uint_t mcache_line_size_bytes;

	struct {
		dml_bool_t UseNewDCN401SOCParameters;

Annotation

Immediate include surface: `display_mode_lib_defines.h`, `dml_top_display_cfg_types.h`.
Detected declarations: `struct soc_state_bounding_box_st`, `struct soc_bounding_box_st`, `struct ip_params_st`, `struct DmlPipe`, `struct Watermarks`, `struct SOCParametersList`, `struct dml_plane_cfg_st`, `struct dml_surface_cfg_st`, `struct dml_timing_cfg_st`, `struct dml_output_cfg_st`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.