drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c
Extension
.c
Size
30843 bytes
Lines
575
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (is_phantom_pipe) {
			detile_buf_plane1_addr = (dml_uint_t)((1024.0*1024.0) / 2.0 / 1024.0); // half to chroma
		} else {
			if (stored_swath_l_bytes / stored_swath_c_bytes <= 1.5) {
				detile_buf_plane1_addr = (dml_uint_t)(detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma
#ifdef __DML_VBA_DEBUG__
				dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d (1/2 to chroma)\n", __func__, detile_buf_plane1_addr);
#endif
			} else {
				detile_buf_plane1_addr = (dml_uint_t)(dml_round_to_multiple((dml_uint_t)((2.0 * detile_buf_size_in_bytes) / 3.0), 1024, 0) / 1024.0); // 2/3 to luma
#ifdef __DML_VBA_DEBUG__
				dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d (1/3 chroma)\n", __func__, detile_buf_plane1_addr);
#endif
			}
		}
	}
	rq_regs->plane1_base_address = detile_buf_plane1_addr;

#ifdef __DML_VBA_DEBUG__
	dml_print("DML_DLG: %s: is_phantom_pipe = %d\n", __func__, is_phantom_pipe);
	dml_print("DML_DLG: %s: stored_swath_l_bytes = %f\n", __func__, stored_swath_l_bytes);
	dml_print("DML_DLG: %s: stored_swath_c_bytes = %f\n", __func__, stored_swath_c_bytes);
	dml_print("DML_DLG: %s: detile_buf_size_in_bytes = %d\n", __func__, detile_buf_size_in_bytes);
	dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d\n", __func__, detile_buf_plane1_addr);
	dml_print("DML_DLG: %s: plane1_base_address = %d\n", __func__, rq_regs->plane1_base_address);
#endif
	dml_print_rq_regs_st(rq_regs);
	dml_print("DML_DLG::%s: Calculation for pipe[%d] done\n", __func__, pipe_idx);
}

// Note: currently taken in as is.
// Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma.


void dml_rq_dlg_get_dlg_reg(dml_display_dlg_regs_st		   *disp_dlg_regs,
	dml_display_ttu_regs_st		   *disp_ttu_regs,
							struct display_mode_lib_st *mode_lib,
							const dml_uint_t			pipe_idx)
{
	dml_uint_t					plane_idx		= dml_get_plane_idx(mode_lib, pipe_idx);
	enum dml_source_format_class	source_format	= mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[plane_idx];
	struct dml_timing_cfg_st		   *timing		   = &mode_lib->ms.cache_display_cfg.timing;
	struct dml_plane_cfg_st			   *plane		   = &mode_lib->ms.cache_display_cfg.plane;
	struct dml_hw_resource_st		   *hw			   = &mode_lib->ms.cache_display_cfg.hw;
	dml_bool_t dual_plane						= is_dual_plane(source_format);
	dml_uint_t num_cursors						= plane->NumberOfCursors[plane_idx];
	enum dml_odm_mode				odm_mode		= hw->ODMMode[plane_idx];

	dml_uint_t	  htotal				= timing->HTotal[plane_idx];
	dml_uint_t	  hactive				= timing->HActive[plane_idx];
	dml_uint_t	  hblank_end			= timing->HBlankEnd[plane_idx];
	dml_uint_t	  vblank_end			= timing->VBlankEnd[plane_idx];
	dml_bool_t	  interlaced			= timing->Interlace[plane_idx];
	dml_float_t   pclk_freq_in_mhz		= (dml_float_t) timing->PixelClock[plane_idx];
	dml_float_t   refclk_freq_in_mhz	= (hw->DLGRefClkFreqMHz > 0) ? (dml_float_t) hw->DLGRefClkFreqMHz : mode_lib->soc.refclk_mhz;
	dml_float_t   ref_freq_to_pix_freq	= refclk_freq_in_mhz / pclk_freq_in_mhz;

	dml_uint_t vready_after_vcount0;

	dml_uint_t dst_x_after_scaler;
	dml_uint_t dst_y_after_scaler;

	dml_float_t dst_y_prefetch;
	dml_float_t dst_y_per_vm_vblank;
	dml_float_t dst_y_per_row_vblank;
	dml_float_t dst_y_per_vm_flip;
	dml_float_t dst_y_per_row_flip;

	dml_float_t max_dst_y_per_vm_vblank = 32.0;		//U5.2
	dml_float_t max_dst_y_per_row_vblank = 16.0;	//U4.2

	dml_float_t vratio_pre_l;
	dml_float_t vratio_pre_c;

	dml_float_t refcyc_per_line_delivery_pre_l;
	dml_float_t refcyc_per_line_delivery_l;
	dml_float_t refcyc_per_line_delivery_pre_c = 0.;
	dml_float_t refcyc_per_line_delivery_c = 0.;
	dml_float_t refcyc_per_req_delivery_pre_l;
	dml_float_t refcyc_per_req_delivery_l;
	dml_float_t refcyc_per_req_delivery_pre_c = 0.;
	dml_float_t refcyc_per_req_delivery_c	  = 0.;
	dml_float_t refcyc_per_req_delivery_pre_cur0 = 0.;
	dml_float_t refcyc_per_req_delivery_cur0 = 0.;

	dml_float_t dst_y_per_pte_row_nom_l;
	dml_float_t dst_y_per_pte_row_nom_c;
	dml_float_t dst_y_per_meta_row_nom_l;
	dml_float_t dst_y_per_meta_row_nom_c;
	dml_float_t refcyc_per_pte_group_nom_l;

Annotation

Implementation Notes