drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h- Extension
.h- Size
- 5809 bytes
- Lines
- 158
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dml2_dc_types.hdisplay_mode_core.hdml2_wrapper.hdml2_policy.hdml_top.hdml21_wrapper.h
Detected Declarations
struct dml2_wrapper_optimize_configuration_paramsstruct dml2_calculate_lowest_supported_state_for_temp_read_scratchstruct dml2_create_scratchstruct dml2_calculate_rq_and_dlg_params_scratchstruct dml2_dml_to_dc_pipe_mappingstruct dml2_wrapper_scratchstruct dml2_helper_det_policy_scratchstruct prepare_mcache_programming_localsstruct dml21_wrapper_scratchstruct dml2_pipe_combine_factorstruct dml2_pipe_combine_scratchstruct dml2_contextenum dml2_architecture
Annotated Snippet
struct dml2_wrapper_optimize_configuration_params {
struct display_mode_lib_st *dml_core_ctx;
struct dml2_configuration_options *config;
struct ip_params_st *ip_params;
struct dml_display_cfg_st *cur_display_config;
struct dml_display_cfg_st *new_display_config;
const struct dml_mode_support_info_st *cur_mode_support_info;
struct dml_mode_eval_policy_st *cur_policy;
struct dml_mode_eval_policy_st *new_policy;
};
struct dml2_calculate_lowest_supported_state_for_temp_read_scratch {
struct dml_mode_support_info_st evaluation_info;
dml_float_t uclk_change_latencies[__DML_MAX_STATE_ARRAY_SIZE__];
struct dml_display_cfg_st cur_display_config;
struct dml_display_cfg_st new_display_config;
struct dml_mode_eval_policy_st new_policy;
struct dml_mode_eval_policy_st cur_policy;
};
struct dml2_create_scratch {
struct dml2_policy_build_synthetic_soc_states_scratch build_synthetic_socbb_scratch;
struct soc_states_st in_states;
};
struct dml2_calculate_rq_and_dlg_params_scratch {
struct _vcs_dpi_dml_display_rq_regs_st rq_regs;
struct _vcs_dpi_dml_display_dlg_regs_st disp_dlg_regs;
struct _vcs_dpi_dml_display_ttu_regs_st disp_ttu_regs;
};
#define __DML2_WRAPPER_MAX_STREAMS_PLANES__ 6
struct dml2_dml_to_dc_pipe_mapping {
unsigned int disp_cfg_to_stream_id[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
bool disp_cfg_to_stream_id_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
unsigned int disp_cfg_to_plane_id[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
bool disp_cfg_to_plane_id_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
unsigned int dml_pipe_idx_to_stream_id[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
bool dml_pipe_idx_to_stream_id_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
unsigned int dml_pipe_idx_to_plane_id[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
bool dml_pipe_idx_to_plane_id_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
unsigned int dml_pipe_idx_to_plane_index[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
bool dml_pipe_idx_to_plane_index_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
};
struct dml2_wrapper_scratch {
struct dml_display_cfg_st cur_display_config;
struct dml_display_cfg_st new_display_config;
struct dml_mode_eval_policy_st new_policy;
struct dml_mode_eval_policy_st cur_policy;
struct dml_mode_support_info_st mode_support_info;
struct dml_mode_support_ex_params_st mode_support_params;
struct dummy_pstate_entry dummy_pstate_table[4];
struct dml2_create_scratch create_scratch;
struct dml2_calculate_lowest_supported_state_for_temp_read_scratch dml2_calculate_lowest_supported_state_for_temp_read_scratch;
struct dml2_calculate_rq_and_dlg_params_scratch calculate_rq_and_dlg_params_scratch;
struct dml2_wrapper_optimize_configuration_params optimize_configuration_params;
struct dml2_policy_build_synthetic_soc_states_params build_synthetic_socbb_params;
struct dml2_dml_to_dc_pipe_mapping dml_to_dc_pipe_mapping;
bool enable_flexible_pipe_mapping;
bool plane_duplicate_exists;
int hpo_stream_to_link_encoder_mapping[MAX_HPO_DP2_ENCODERS];
};
struct dml2_helper_det_policy_scratch {
int dpps_per_surface[MAX_PLANES];
};
enum dml2_architecture {
dml2_architecture_20,
dml2_architecture_21
};
struct prepare_mcache_programming_locals {
struct dml2_build_mcache_programming_in_out build_mcache_programming_params;
};
struct dml21_wrapper_scratch {
struct prepare_mcache_programming_locals prepare_mcache_locals;
struct pipe_ctx temp_pipe;
};
struct dml2_pipe_combine_factor {
unsigned int source;
unsigned int target;
Annotation
- Immediate include surface: `dml2_dc_types.h`, `display_mode_core.h`, `dml2_wrapper.h`, `dml2_policy.h`, `dml_top.h`, `dml21_wrapper.h`.
- Detected declarations: `struct dml2_wrapper_optimize_configuration_params`, `struct dml2_calculate_lowest_supported_state_for_temp_read_scratch`, `struct dml2_create_scratch`, `struct dml2_calculate_rq_and_dlg_params_scratch`, `struct dml2_dml_to_dc_pipe_mapping`, `struct dml2_wrapper_scratch`, `struct dml2_helper_det_policy_scratch`, `struct prepare_mcache_programming_locals`, `struct dml21_wrapper_scratch`, `struct dml2_pipe_combine_factor`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.