drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c
Extension
.c
Size
12764 bytes
Lines
312
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

while (net_bw_of_new_state > calculate_net_bw_in_mbytes_sec(socbb, &table->state_array[index])) {
			index++;
			if (index >= (int) table->num_states)
				break;
		}

		for (i = table->num_states; i > index; i--) {
			table->state_array[i] = table->state_array[i - 1];
		}
		//ASSERT(index < MAX_CLK_TABLE_SIZE);
	}

	table->state_array[index] = *entry;
	table->state_array[index].dcfclk_mhz = (int)entry->dcfclk_mhz;
	table->state_array[index].fabricclk_mhz = (int)entry->fabricclk_mhz;
	table->state_array[index].dram_speed_mts = (int)entry->dram_speed_mts;
	table->num_states++;
}

static void remove_entry_from_table_at_index(struct soc_states_st *table,
	unsigned int index)
{
	int i;

	if (table->num_states == 0)
		return;

	for (i = index; i < (int) table->num_states - 1; i++) {
		table->state_array[i] = table->state_array[i + 1];
	}
	memset(&table->state_array[--table->num_states], 0, sizeof(struct soc_state_bounding_box_st));
}

int dml2_policy_build_synthetic_soc_states(struct dml2_policy_build_synthetic_soc_states_scratch *s,
	struct dml2_policy_build_synthetic_soc_states_params *p)
{
	int i, j;
	unsigned int min_fclk_mhz = (unsigned int)p->in_states->state_array[0].fabricclk_mhz;
	unsigned int min_dcfclk_mhz = (unsigned int)p->in_states->state_array[0].dcfclk_mhz;
	unsigned int min_socclk_mhz = (unsigned int)p->in_states->state_array[0].socclk_mhz;

	int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0,
		max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0,
		max_uclk_mhz = 0, max_socclk_mhz = 0;

	int num_uclk_dpms = 0, num_fclk_dpms = 0;

	for (i = 0; i < __DML_MAX_STATE_ARRAY_SIZE__; i++) {
		if (p->in_states->state_array[i].dcfclk_mhz > max_dcfclk_mhz)
			max_dcfclk_mhz = (int) p->in_states->state_array[i].dcfclk_mhz;
		if (p->in_states->state_array[i].fabricclk_mhz > max_fclk_mhz)
			max_fclk_mhz = (int) p->in_states->state_array[i].fabricclk_mhz;
		if (p->in_states->state_array[i].socclk_mhz > max_socclk_mhz)
			max_socclk_mhz = (int) p->in_states->state_array[i].socclk_mhz;
		if (p->in_states->state_array[i].dram_speed_mts > max_uclk_mhz)
			max_uclk_mhz = (int) p->in_states->state_array[i].dram_speed_mts;
		if (p->in_states->state_array[i].dispclk_mhz > max_dispclk_mhz)
			max_dispclk_mhz = (int) p->in_states->state_array[i].dispclk_mhz;
		if (p->in_states->state_array[i].dppclk_mhz > max_dppclk_mhz)
			max_dppclk_mhz = (int) p->in_states->state_array[i].dppclk_mhz;
		if (p->in_states->state_array[i].phyclk_mhz > max_phyclk_mhz)
			max_phyclk_mhz = (int)p->in_states->state_array[i].phyclk_mhz;
		if (p->in_states->state_array[i].dtbclk_mhz > max_dtbclk_mhz)
			max_dtbclk_mhz = (int)p->in_states->state_array[i].dtbclk_mhz;

		if (p->in_states->state_array[i].fabricclk_mhz > 0)
			num_fclk_dpms++;
		if (p->in_states->state_array[i].dram_speed_mts > 0)
			num_uclk_dpms++;
	}

	if (!max_dcfclk_mhz || !max_dispclk_mhz || !max_dppclk_mhz || !max_phyclk_mhz || !max_dtbclk_mhz)
		return -1;

	p->out_states->num_states = 0;

	s->entry = p->in_states->state_array[0];

	s->entry.dispclk_mhz = max_dispclk_mhz;
	s->entry.dppclk_mhz = max_dppclk_mhz;
	s->entry.dtbclk_mhz = max_dtbclk_mhz;
	s->entry.phyclk_mhz = max_phyclk_mhz;

	s->entry.dscclk_mhz = max_dispclk_mhz / 3;
	s->entry.phyclk_mhz = max_phyclk_mhz;
	s->entry.dtbclk_mhz = max_dtbclk_mhz;

	// Insert all the DCFCLK STAs first
	for (i = 0; i < p->num_dcfclk_stas; i++) {
		s->entry.dcfclk_mhz = p->dcfclk_stas_mhz[i];

Annotation

Implementation Notes