drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
Extension
.c
Size
69358 bytes
Lines
1539
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (dml2->config.bbox_overrides.sr_exit_latency_us) {
			p->in_states->state_array[i].sr_exit_time_us =
				dml2->config.bbox_overrides.sr_exit_latency_us;
		}

		if (dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us) {
			p->in_states->state_array[i].sr_enter_plus_exit_time_us =
				dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us;
		}

		if (dml2->config.bbox_overrides.sr_exit_z8_time_us) {
			p->in_states->state_array[i].sr_exit_z8_time_us =
				dml2->config.bbox_overrides.sr_exit_z8_time_us;
		}

		if (dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us) {
			p->in_states->state_array[i].sr_enter_plus_exit_z8_time_us =
				dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us;
		}

		if (dml2->config.bbox_overrides.urgent_latency_us) {
			p->in_states->state_array[i].urgent_latency_pixel_data_only_us =
				dml2->config.bbox_overrides.urgent_latency_us;
		}

		if (dml2->config.bbox_overrides.dram_clock_change_latency_us) {
			p->in_states->state_array[i].dram_clock_change_latency_us =
				dml2->config.bbox_overrides.dram_clock_change_latency_us;
		}

		if (dml2->config.bbox_overrides.fclk_change_latency_us) {
			p->in_states->state_array[i].fclk_change_latency_us =
				dml2->config.bbox_overrides.fclk_change_latency_us;
		}
	}

	/* DCFCLK stas values are project specific */
	if ((dml2->v20.dml_core_ctx.project == dml_project_dcn32) ||
		(dml2->v20.dml_core_ctx.project == dml_project_dcn321)) {
		p->dcfclk_stas_mhz[0] = (int)p->in_states->state_array[0].dcfclk_mhz;
		p->dcfclk_stas_mhz[1] = 615;
		p->dcfclk_stas_mhz[2] = 906;
		p->dcfclk_stas_mhz[3] = 1324;
		p->dcfclk_stas_mhz[4] = (int)p->in_states->state_array[1].dcfclk_mhz;
	} else if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 &&
			dml2->v20.dml_core_ctx.project != dml_project_dcn36 &&
			dml2->v20.dml_core_ctx.project != dml_project_dcn351) {
		p->dcfclk_stas_mhz[0] = 300;
		p->dcfclk_stas_mhz[1] = 615;
		p->dcfclk_stas_mhz[2] = 906;
		p->dcfclk_stas_mhz[3] = 1324;
		p->dcfclk_stas_mhz[4] = 1500;
	}
	/* Copy clocks tables entries, if available */
	if (dml2->config.bbox_overrides.clks_table.num_states) {
		p->in_states->num_states = dml2->config.bbox_overrides.clks_table.num_states;
		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels; i++) {
			p->in_states->state_array[i].dcfclk_mhz = dml2->config.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz;
		}

		p->dcfclk_stas_mhz[0] = dml2->config.bbox_overrides.clks_table.clk_entries[0].dcfclk_mhz;
		if (i > 1)
			p->dcfclk_stas_mhz[4] = dml2->config.bbox_overrides.clks_table.clk_entries[i-1].dcfclk_mhz;

		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels; i++) {
			p->in_states->state_array[i].fabricclk_mhz =
				dml2->config.bbox_overrides.clks_table.clk_entries[i].fclk_mhz;
		}

		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels; i++) {
			p->in_states->state_array[i].dram_speed_mts =
				dml2->config.bbox_overrides.clks_table.clk_entries[i].memclk_mhz * transactions_per_mem_clock;
		}

		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels; i++) {
			p->in_states->state_array[i].socclk_mhz =
				dml2->config.bbox_overrides.clks_table.clk_entries[i].socclk_mhz;
		}

		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels; i++) {
			if (dml2->config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz > 0)
				p->in_states->state_array[i].dtbclk_mhz =
					dml2->config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz;
		}

		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels; i++) {
			p->in_states->state_array[i].dispclk_mhz =
				dml2->config.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz;
			p->in_states->state_array[i].dppclk_mhz =
				dml2->config.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz;

Annotation

Implementation Notes