drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h- Extension
.h- Size
- 7023 bytes
- Lines
- 150
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
os_types.hdml2_dc_types.h
Detected Declarations
struct dcstruct dml_timing_cfg_ststruct dml2_dcn_clocksstruct dc_state
Annotated Snippet
#ifndef _DML2_UTILS_H_
#define _DML2_UTILS_H_
#include "os_types.h"
#include "dml2_dc_types.h"
struct dc;
struct dml_timing_cfg_st;
struct dml2_dcn_clocks;
struct dc_state;
void dml2_util_copy_dml_timing(struct dml_timing_cfg_st *dml_timing_array, unsigned int dst_index, unsigned int src_index);
void dml2_util_copy_dml_plane(struct dml_plane_cfg_st *dml_plane_array, unsigned int dst_index, unsigned int src_index);
void dml2_util_copy_dml_surface(struct dml_surface_cfg_st *dml_surface_array, unsigned int dst_index, unsigned int src_index);
void dml2_util_copy_dml_output(struct dml_output_cfg_st *dml_output_array, unsigned int dst_index, unsigned int src_index);
unsigned int dml2_util_get_maximum_odm_combine_for_output(bool force_odm_4to1, enum dml_output_encoder_class encoder, bool dsc_enabled);
void dml2_copy_clocks_to_dc_state(struct dml2_dcn_clocks *out_clks, struct dc_state *context);
void dml2_extract_watermark_set(struct dcn_watermarks *watermark, struct display_mode_lib_st *dml_core_ctx);
void dml2_extract_writeback_wm(struct dc_state *context, struct display_mode_lib_st *dml_core_ctx);
int dml2_helper_find_dml_pipe_idx_by_stream_id(struct dml2_context *ctx, unsigned int stream_id);
bool is_dtbclk_required(const struct dc *dc, struct dc_state *context);
bool dml2_is_stereo_timing(const struct dc_stream_state *stream);
unsigned int dml2_calc_max_scaled_time(
unsigned int time_per_pixel,
enum mmhubbub_wbif_mode mode,
unsigned int urgent_watermark);
/*
* dml2_dc_construct_pipes - This function will determine if we need additional pipes based
* on the DML calculated outputs for MPC, ODM and allocate them as necessary. This function
* could be called after in dml_validate_build_resource after dml_mode_pragramming like :
* {
* ...
* map_hw_resources(&s->cur_display_config, &s->mode_support_info);
* result = dml_mode_programming(&in_ctx->dml_core_ctx, s->mode_support_params.out_lowest_state_idx, &s->cur_display_config, true);
* dml2_dc_construct_pipes(in_display_state, s->mode_support_info, out_hw_context);
* ...
* }
*
* @context: To obtain res_ctx and read other information like stream ID etc.
* @dml_mode_support_st : To get the ODM, MPC outputs as determined by the DML.
* @out_hw_context : Handle to the new hardware context.
*
*
* Return: None.
*/
void dml2_dc_construct_pipes(struct dc_state *context, struct dml_mode_support_info_st *dml_mode_support_st,
struct resource_context *out_hw_context);
/*
* dml2_predict_pipe_split - This function is the dml2 version of predict split pipe. It predicts a
* if pipe split is required or not and returns the output as a bool.
* @context : dc_state.
* @pipe : old_index is the index of the pipe as derived from pipe_idx.
* @index : index of the pipe
*
*
* Return: Returns the result in boolean.
*/
bool dml2_predict_pipe_split(struct dc_state *context, display_pipe_params_st pipe, int index);
/*
* dml2_build_mapped_resource - This function is the dml2 version of build_mapped_resource.
* In case of ODM, we need to build pipe hardware params again as done in dcn20_build_mapped_resource.
* @dc : struct dc
* @context : struct dc_state.
* @stream : stream whoose corresponding pipe params need to be modified.
*
*
* Return: Returns DC_OK if successful.
*/
enum dc_status dml2_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);
/*
* dml2_extract_rq_regs - This function will extract information needed for struct _vcs_dpi_display_rq_regs_st
* and populate it.
* @context: To obtain and populate the res_ctx->pipe_ctx->rq_regs with DML outputs.
* @support : This structure has the DML intermediate outputs required to populate rq_regs.
*
*
* Return: None.
*/
/*
* dml2_calculate_rq_and_dlg_params - This function will call into DML2 functions needed
* for populating rq, ttu and dlg param structures and populate it.
* @dc : struct dc
* @context : dc_state provides a handle to selectively populate pipe_ctx
* @out_new_hw_state: To obtain and populate the rq, dlg and ttu regs in
* out_new_hw_state->pipe_ctx with DML outputs.
Annotation
- Immediate include surface: `os_types.h`, `dml2_dc_types.h`.
- Detected declarations: `struct dc`, `struct dml_timing_cfg_st`, `struct dml2_dcn_clocks`, `struct dc_state`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.