drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h- Extension
.h- Size
- 12088 bytes
- Lines
- 321
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
os_types.h
Detected Declarations
struct dml2_contextstruct display_mode_lib_ststruct dcstruct pipe_ctxstruct dc_plane_statestruct dc_sinkstruct dc_stream_statestruct resource_contextstruct display_stream_compressorstruct dc_mcache_paramsstruct dml2_soc_mall_infostruct dml2_dcn_clocksstruct dml2_dc_callbacksstruct dml2_dc_svp_callbacksstruct dml2_clks_table_entrystruct dml2_clks_num_entriesstruct dml2_clks_limit_tablestruct dml2_soc_bbox_overridesstruct dml2_configuration_optionsenum dml2_force_pstate_methods
Annotated Snippet
struct dml2_soc_mall_info {
// Cache line size of 0 means MALL is not enabled/present
unsigned int cache_line_size_bytes;
unsigned int cache_num_ways;
unsigned int max_cab_allocation_bytes;
unsigned int mblk_width_pixels;
unsigned int mblk_size_bytes;
unsigned int mblk_height_4bpe_pixels;
unsigned int mblk_height_8bpe_pixels;
};
// Output of DML2 for clock requirements
struct dml2_dcn_clocks {
unsigned int dispclk_khz;
unsigned int dcfclk_khz;
unsigned int fclk_khz;
unsigned int uclk_mts;
unsigned int phyclk_khz;
unsigned int socclk_khz;
unsigned int ref_dtbclk_khz;
bool p_state_supported;
unsigned int cab_num_ways_required;
unsigned int dcfclk_khz_ds;
};
struct dml2_dc_callbacks {
struct dc *dc;
bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx);
void (*build_test_pattern_params)(struct resource_context *res_ctx, struct pipe_ctx *otg_master);
bool (*can_support_mclk_switch_using_fw_based_vblank_stretch)(struct dc *dc, struct dc_state *context);
bool (*acquire_secondary_pipe_for_mpc_odm)(const struct dc *dc, struct dc_state *state, struct pipe_ctx *pri_pipe, struct pipe_ctx *sec_pipe, bool odm);
bool (*update_pipes_for_stream_with_slice_count)(
struct dc_state *new_ctx,
const struct dc_state *cur_ctx,
const struct resource_pool *pool,
const struct dc_stream_state *stream,
int new_slice_count);
bool (*update_pipes_for_plane_with_slice_count)(
struct dc_state *new_ctx,
const struct dc_state *cur_ctx,
const struct resource_pool *pool,
const struct dc_plane_state *plane,
int slice_count);
int (*get_odm_slice_index)(const struct pipe_ctx *opp_head);
int (*get_odm_slice_count)(const struct pipe_ctx *opp_head);
int (*get_mpc_slice_index)(const struct pipe_ctx *dpp_pipe);
int (*get_mpc_slice_count)(const struct pipe_ctx *dpp_pipe);
struct pipe_ctx *(*get_opp_head)(const struct pipe_ctx *pipe_ctx);
struct pipe_ctx *(*get_otg_master_for_stream)(
struct resource_context *res_ctx,
const struct dc_stream_state *stream);
int (*get_opp_heads_for_otg_master)(const struct pipe_ctx *otg_master,
struct resource_context *res_ctx,
struct pipe_ctx *opp_heads[MAX_PIPES]);
int (*get_dpp_pipes_for_plane)(const struct dc_plane_state *plane,
struct resource_context *res_ctx,
struct pipe_ctx *dpp_pipes[MAX_PIPES]);
struct dc_stream_status *(*get_stream_status)(
struct dc_state *state,
const struct dc_stream_state *stream);
struct dc_stream_state *(*get_stream_from_id)(const struct dc_state *state, unsigned int id);
unsigned int (*get_max_flickerless_instant_vtotal_increase)(
struct dc_stream_state *stream,
bool is_gaming);
bool (*allocate_mcache)(struct dc_state *context, const struct dc_mcache_params *mcache_params);
};
struct dml2_dc_svp_callbacks {
struct dc *dc;
bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx);
struct dc_stream_state* (*create_phantom_stream)(const struct dc *dc,
struct dc_state *state,
struct dc_stream_state *main_stream);
struct dc_plane_state* (*create_phantom_plane)(const struct dc *dc,
struct dc_state *state,
struct dc_plane_state *main_plane);
enum dc_status (*add_phantom_stream)(const struct dc *dc,
struct dc_state *state,
struct dc_stream_state *phantom_stream,
struct dc_stream_state *main_stream);
bool (*add_phantom_plane)(const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, struct dc_state *context);
bool (*remove_phantom_plane)(const struct dc *dc,
struct dc_stream_state *stream,
struct dc_plane_state *plane_state,
struct dc_state *context);
enum dc_status (*remove_phantom_stream)(const struct dc *dc,
struct dc_state *state,
struct dc_stream_state *stream);
void (*release_phantom_plane)(const struct dc *dc,
Annotation
- Immediate include surface: `os_types.h`.
- Detected declarations: `struct dml2_context`, `struct display_mode_lib_st`, `struct dc`, `struct pipe_ctx`, `struct dc_plane_state`, `struct dc_sink`, `struct dc_stream_state`, `struct resource_context`, `struct display_stream_compressor`, `struct dc_mcache_params`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.