drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c- Extension
.c- Size
- 20970 bytes
- Lines
- 535
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dml2_internal_shared_types.hdml21_translation_helper.hdml2_internal_types.hdml21_utils.hdml2_dc_resource_mgmt.hdml2_core_dcn4_calcs.h
Detected Declarations
function dml21_helper_find_dml_pipe_idx_by_stream_idfunction dml21_find_dml_pipe_idx_by_plane_idfunction dml21_get_plane_idfunction dml21_get_dc_plane_idx_from_plane_idfunction find_valid_pipe_idx_for_stream_indexfunction find_pipe_regs_idxfunction dml21_find_dc_pipes_for_planefunction dml21_pipe_populate_global_syncfunction dml21_populate_mall_allocation_sizefunction check_dp2p0_output_encoderfunction is_sub_vp_enabledfunction dml21_program_dc_pipefunction dml21_handle_phantom_streams_planesfunction dml21_build_fams2_stream_programming_v2function dml21_build_fams2_programmingfunction dml21_is_plane1_enabled
Annotated Snippet
if (state->stream_status[i].plane_states[j] == plane) {
*plane_id = (i << 16) | j;
return true;
}
}
}
return false;
}
unsigned int dml21_get_dc_plane_idx_from_plane_id(unsigned int plane_id)
{
return 0xffff & plane_id;
}
void find_valid_pipe_idx_for_stream_index(const struct dml2_context *dml_ctx, unsigned int *dml_pipe_idx, unsigned int stream_index)
{
unsigned int i = 0;
for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
if (dml_ctx->v21.mode_programming.programming->plane_programming[i].plane_descriptor->stream_index == stream_index) {
*dml_pipe_idx = i;
return;
}
}
}
void find_pipe_regs_idx(const struct dml2_context *dml_ctx,
struct pipe_ctx *pipe, unsigned int *pipe_regs_idx)
{
struct pipe_ctx *opp_head = dml_ctx->config.callbacks.get_opp_head(pipe);
*pipe_regs_idx = dml_ctx->config.callbacks.get_odm_slice_index(opp_head);
if (pipe->plane_state)
*pipe_regs_idx += dml_ctx->config.callbacks.get_mpc_slice_index(pipe);
}
/* places pipe references into pipes arrays and returns number of pipes */
int dml21_find_dc_pipes_for_plane(const struct dc *in_dc,
struct dc_state *context,
struct dml2_context *dml_ctx,
struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],
struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],
int dml_plane_idx)
{
(void)in_dc;
unsigned int dml_stream_index;
unsigned int main_stream_id;
unsigned int dc_plane_index;
struct dc_stream_state *dc_main_stream;
struct dc_stream_status *dc_main_stream_status;
struct dc_plane_state *dc_main_plane;
struct dc_stream_state *dc_phantom_stream;
struct dc_stream_status *dc_phantom_stream_status;
struct dc_plane_state *dc_phantom_plane;
int num_pipes = 0;
memset(dc_main_pipes, 0, sizeof(struct pipe_ctx *) * __DML2_WRAPPER_MAX_STREAMS_PLANES__);
memset(dc_phantom_pipes, 0, sizeof(struct pipe_ctx *) * __DML2_WRAPPER_MAX_STREAMS_PLANES__);
dml_stream_index = dml_ctx->v21.mode_programming.programming->plane_programming[dml_plane_idx].plane_descriptor->stream_index;
main_stream_id = dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_stream_index];
dc_main_stream = dml_ctx->config.callbacks.get_stream_from_id(context, main_stream_id);
dc_main_stream_status = dml_ctx->config.callbacks.get_stream_status(context, dc_main_stream);
if (!dc_main_stream_status)
return num_pipes;
/* find main plane based on id */
dc_plane_index = dml21_get_dc_plane_idx_from_plane_id(dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[dml_plane_idx]);
dc_main_plane = dc_main_stream_status->plane_states[dc_plane_index];
if (dc_main_plane) {
num_pipes = dml_ctx->config.callbacks.get_dpp_pipes_for_plane(dc_main_plane, &context->res_ctx, dc_main_pipes);
} else {
/* stream was configured with dummy plane, so get pipes from opp head */
struct pipe_ctx *otg_master_pipe = dml_ctx->config.callbacks.get_otg_master_for_stream(&context->res_ctx, dc_main_stream);
if (otg_master_pipe != NULL)
num_pipes = dml_ctx->config.callbacks.get_opp_heads_for_otg_master(otg_master_pipe, &context->res_ctx, dc_main_pipes);
}
/* if phantom exists, find associated pipes */
dc_phantom_stream = dml_ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, dc_main_stream);
if (dc_phantom_stream && num_pipes > 0) {
dc_phantom_stream_status = dml_ctx->config.callbacks.get_stream_status(context, dc_phantom_stream);
if (dc_phantom_stream_status) {
/* phantom plane will have same index as main */
dc_phantom_plane = dc_phantom_stream_status->plane_states[dc_plane_index];
Annotation
- Immediate include surface: `dml2_internal_shared_types.h`, `dml21_translation_helper.h`, `dml2_internal_types.h`, `dml21_utils.h`, `dml2_dc_resource_mgmt.h`, `dml2_core_dcn4_calcs.h`.
- Detected declarations: `function dml21_helper_find_dml_pipe_idx_by_stream_id`, `function dml21_find_dml_pipe_idx_by_plane_id`, `function dml21_get_plane_id`, `function dml21_get_dc_plane_idx_from_plane_id`, `function find_valid_pipe_idx_for_stream_index`, `function find_pipe_regs_idx`, `function dml21_find_dc_pipes_for_plane`, `function dml21_pipe_populate_global_sync`, `function dml21_populate_mall_allocation_size`, `function check_dp2p0_output_encoder`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.