drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42b_soc_bb.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42b_soc_bb.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42b_soc_bb.h
Extension
.h
Size
5919 bytes
Lines
228
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: MIT
//
// Copyright 2026 Advanced Micro Devices, Inc.

#ifndef __DML_DML_DCN42B_SOC_BB__
#define __DML_DML_DCN42B_SOC_BB__

#include "dml_top_soc_parameter_types.h"

/* DCN42B Bounding Box values */
static const struct dml2_soc_qos_parameters dml_dcn42b_variant_a_soc_qos_params = {
	.derate_table = {
		.system_active_urgent = {
			.dram_derate_percent_pixel = 65,
			.dram_derate_percent_vm = 30,
			.dram_derate_percent_pixel_and_vm = 60,
			.fclk_derate_percent = 80,
			.dcfclk_derate_percent = 80,
		},
		.system_active_average = {
			.dram_derate_percent_pixel = 30,
			.dram_derate_percent_vm = 30,
			.dram_derate_percent_pixel_and_vm = 30,
			.fclk_derate_percent = 60,
			.dcfclk_derate_percent = 60,
		},
		.dcn_mall_prefetch_urgent = {
			.dram_derate_percent_pixel = 65,
			.dram_derate_percent_vm = 30,
			.dram_derate_percent_pixel_and_vm = 60,
			.fclk_derate_percent = 80,
			.dcfclk_derate_percent = 80,
		},
		.dcn_mall_prefetch_average = {
			.dram_derate_percent_pixel = 30,
			.dram_derate_percent_vm = 30,
			.dram_derate_percent_pixel_and_vm = 30,
			.fclk_derate_percent = 60,
			.dcfclk_derate_percent = 60,
		},
		.system_idle_average = {
			.dram_derate_percent_pixel = 30,
			.dram_derate_percent_vm = 30,
			.dram_derate_percent_pixel_and_vm = 30,
			.fclk_derate_percent = 60,
			.dcfclk_derate_percent = 60,
		},
	},
	.writeback = {
		.base_latency_us = 12,
		.scaling_factor_us = 0,
		.scaling_factor_mhz = 0,
	},
	.qos_params = {
		.dcn32x = {
			.loaded_round_trip_latency_fclk_cycles = 106,
			.urgent_latency_us = {
				.base_latency_us = 4,
				.base_latency_pixel_vm_us = 4,
				.base_latency_vm_us = 4,
				.scaling_factor_fclk_us = 0,
				.scaling_factor_mhz = 0,
			},
			.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
			.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
			.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
		},
	},
	.qos_type = dml2_qos_param_type_dcn3,
};

static const struct dml2_soc_bb dml2_socbb_dcn42b = {
	.clk_table = {
		.wck_ratio = {
				.clk_values_khz = {2},
		},
		.uclk = {
				.clk_values_khz = {400000},
				.num_clk_values = 1,
		},
		.fclk = {
				.clk_values_khz = {1600000},
				.num_clk_values = 1,
		},
		.dcfclk = {
				.clk_values_khz = {800000},
				.num_clk_values = 1,
		},
		.dispclk = {
				.clk_values_khz = {1200000},

Annotation

Implementation Notes