drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_dchub_registers.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_dchub_registers.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_dchub_registers.h
Extension: .h
Size: 5209 bytes
Lines: 192
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

dml2_external_lib_deps.h

Detected Declarations

struct dml2_display_dlg_regs
struct dml2_display_ttu_regs
struct dml2_display_arb_regs
struct dml2_cursor_dlg_regs
struct dml2_display_plane_rq_regs
struct dml2_display_rq_regs
struct dml2_display_mcache_regs
struct dml2_hubp_pipe_mcache_regs
struct dml2_dchub_per_pipe_register_set
struct dml2_dchub_watermark_regs
struct dml2_dchub_global_register_set
enum dml2_dchub_watermark_reg_set_index

Annotated Snippet

struct dml2_display_dlg_regs {
	uint32_t refcyc_h_blank_end;
	uint32_t dlg_vblank_end;
	uint32_t min_dst_y_next_start;
	uint32_t refcyc_per_htotal;
	uint32_t refcyc_x_after_scaler;
	uint32_t dst_y_after_scaler;
	uint32_t dst_y_prefetch;
	uint32_t dst_y_per_vm_vblank;
	uint32_t dst_y_per_row_vblank;
	uint32_t dst_y_per_vm_flip;
	uint32_t dst_y_per_row_flip;
	uint32_t ref_freq_to_pix_freq;
	uint32_t vratio_prefetch;
	uint32_t vratio_prefetch_c;
	uint32_t refcyc_per_tdlut_group;
	uint32_t refcyc_per_pte_group_vblank_l;
	uint32_t refcyc_per_pte_group_vblank_c;
	uint32_t refcyc_per_pte_group_flip_l;
	uint32_t refcyc_per_pte_group_flip_c;
	uint32_t dst_y_per_pte_row_nom_l;
	uint32_t dst_y_per_pte_row_nom_c;
	uint32_t refcyc_per_pte_group_nom_l;
	uint32_t refcyc_per_pte_group_nom_c;
	uint32_t refcyc_per_line_delivery_pre_l;
	uint32_t refcyc_per_line_delivery_pre_c;
	uint32_t refcyc_per_line_delivery_l;
	uint32_t refcyc_per_line_delivery_c;
	uint32_t refcyc_per_vm_group_vblank;
	uint32_t refcyc_per_vm_group_flip;
	uint32_t refcyc_per_vm_req_vblank;
	uint32_t refcyc_per_vm_req_flip;
	uint32_t dst_y_offset_cur0;
	uint32_t chunk_hdl_adjust_cur0;
	uint32_t vready_after_vcount0;
	uint32_t dst_y_delta_drq_limit;
	uint32_t refcyc_per_vm_dmdata;
	uint32_t dmdata_dl_delta;

	// MRQ
	uint32_t refcyc_per_meta_chunk_vblank_l;
	uint32_t refcyc_per_meta_chunk_vblank_c;
	uint32_t refcyc_per_meta_chunk_flip_l;
	uint32_t refcyc_per_meta_chunk_flip_c;
	uint32_t dst_y_per_meta_row_nom_l;
	uint32_t dst_y_per_meta_row_nom_c;
	uint32_t refcyc_per_meta_chunk_nom_l;
	uint32_t refcyc_per_meta_chunk_nom_c;
};

struct dml2_display_ttu_regs {
	uint32_t qos_level_low_wm;
	uint32_t qos_level_high_wm;
	uint32_t min_ttu_vblank;
	uint32_t qos_level_flip;
	uint32_t refcyc_per_req_delivery_l;
	uint32_t refcyc_per_req_delivery_c;
	uint32_t refcyc_per_req_delivery_cur0;
	uint32_t refcyc_per_req_delivery_pre_l;
	uint32_t refcyc_per_req_delivery_pre_c;
	uint32_t refcyc_per_req_delivery_pre_cur0;
	uint32_t qos_level_fixed_l;
	uint32_t qos_level_fixed_c;
	uint32_t qos_level_fixed_cur0;
	uint32_t qos_ramp_disable_l;
	uint32_t qos_ramp_disable_c;
	uint32_t qos_ramp_disable_cur0;
};

struct dml2_display_arb_regs {
	uint32_t max_req_outstanding;
	uint32_t min_req_outstanding;
	uint32_t sat_level_us;
	uint32_t hvm_max_qos_commit_threshold;
	uint32_t hvm_min_req_outstand_commit_threshold;
	uint32_t compbuf_reserved_space_kbytes;
	uint32_t compbuf_size;
	uint32_t sdpif_request_rate_limit;
	uint32_t allow_sdpif_rate_limit_when_cstate_req;
	uint32_t dcfclk_deep_sleep_hysteresis;
	uint32_t pstate_stall_threshold;
};

struct dml2_cursor_dlg_regs{
	uint32_t dst_x_offset;			   // CURSOR0_DST_X_OFFSET
	uint32_t dst_y_offset;			   // CURSOR0_DST_Y_OFFSET
	uint32_t chunk_hdl_adjust;		   // CURSOR0_CHUNK_HDL_ADJUST

	uint32_t qos_level_fixed;
	uint32_t qos_ramp_disable;

Annotation

Immediate include surface: `dml2_external_lib_deps.h`.
Detected declarations: `struct dml2_display_dlg_regs`, `struct dml2_display_ttu_regs`, `struct dml2_display_arb_regs`, `struct dml2_cursor_dlg_regs`, `struct dml2_display_plane_rq_regs`, `struct dml2_display_rq_regs`, `struct dml2_display_mcache_regs`, `struct dml2_hubp_pipe_mcache_regs`, `struct dml2_dchub_per_pipe_register_set`, `struct dml2_dchub_watermark_regs`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.