drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top.h- Extension
.h- Size
- 1452 bytes
- Lines
- 47
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dml_top_types.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: MIT
//
// Copyright 2024 Advanced Micro Devices, Inc.
#ifndef __DML_TOP_H__
#define __DML_TOP_H__
#include "dml_top_types.h"
/*
* Top Level Interface for DML2
*/
/*
* Returns the size of the DML instance for the caller to allocate
*/
unsigned int dml2_get_instance_size_bytes(void);
/*
* Initializes the DML instance (i.e. with configuration, soc BB, IP params, etc...)
*/
bool dml2_initialize_instance(struct dml2_initialize_instance_in_out *in_out);
/*
* Determines if the input mode is supported (boolean) on the SoC at all. Does not return
* information on how mode should be programmed.
*/
bool dml2_check_mode_supported(struct dml2_check_mode_supported_in_out *in_out);
/*
* Determines the full (optimized) programming for the input mode. Returns minimum
* clocks as well as dchub register programming values for all pipes, additional meta
* such as ODM or MPCC combine factors.
*/
bool dml2_build_mode_programming(struct dml2_build_mode_programming_in_out *in_out);
/*
* Determines the correct per pipe mcache register programming for a valid mode.
* The mcache allocation must have been calculated (successfully) in a previous
* call to dml2_build_mode_programming.
* The actual hubp viewport dimensions be what the actual registers will be
* programmed to (i.e. based on scaler setup).
*/
bool dml2_build_mcache_programming(struct dml2_build_mcache_programming_in_out *in_out);
#endif
Annotation
- Immediate include surface: `dml_top_types.h`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.