drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h
Extension
.h
Size
7078 bytes
Lines
222
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dml2_soc_derate_values {
	unsigned int dram_derate_percent_pixel;
	unsigned int dram_derate_percent_vm;
	unsigned int dram_derate_percent_pixel_and_vm;

	unsigned int fclk_derate_percent;
	unsigned int dcfclk_derate_percent;
};

struct dml2_soc_derates {
	struct dml2_soc_derate_values system_active_urgent;
	struct dml2_soc_derate_values system_active_average;
	struct dml2_soc_derate_values dcn_mall_prefetch_urgent;
	struct dml2_soc_derate_values dcn_mall_prefetch_average;
	struct dml2_soc_derate_values system_idle_average;
};

struct dml2_dcn32x_soc_qos_params {
	struct {
		unsigned int base_latency_us;
		unsigned int base_latency_pixel_vm_us;
		unsigned int base_latency_vm_us;
		unsigned int scaling_factor_fclk_us;
		unsigned int scaling_factor_mhz;
	} urgent_latency_us;

	unsigned int loaded_round_trip_latency_fclk_cycles;
	unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes;
	unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
	unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes;
};

struct dml2_dcn4_uclk_dpm_dependent_qos_params {
	unsigned long minimum_uclk_khz;
	unsigned int urgent_ramp_uclk_cycles;
	unsigned int trip_to_memory_uclk_cycles;
	unsigned int meta_trip_to_memory_uclk_cycles;
	unsigned int maximum_latency_when_urgent_uclk_cycles;
	unsigned int average_latency_when_urgent_uclk_cycles;
	unsigned int maximum_latency_when_non_urgent_uclk_cycles;
	unsigned int average_latency_when_non_urgent_uclk_cycles;
};

struct dml2_dcn4x_soc_qos_params {
	unsigned int df_qos_response_time_fclk_cycles;
	unsigned int max_round_trip_to_furthest_cs_fclk_cycles;
	unsigned int mall_overhead_fclk_cycles;
	unsigned int meta_trip_adder_fclk_cycles;
	unsigned int average_transport_distance_fclk_cycles;
	double umc_urgent_ramp_latency_margin;
	double umc_max_latency_margin;
	double umc_average_latency_margin;
	double fabric_max_transport_latency_margin;
	double fabric_average_transport_latency_margin;
	struct dml2_dcn4_uclk_dpm_dependent_qos_params per_uclk_dpm_params[DML_MAX_CLK_TABLE_SIZE];
};

enum dml2_qos_param_type {
	dml2_qos_param_type_dcn3,
	dml2_qos_param_type_dcn4x
};

struct dml2_soc_qos_parameters {
	struct dml2_soc_derates derate_table;
	struct {
		unsigned int base_latency_us;
		unsigned int scaling_factor_us;
		unsigned int scaling_factor_mhz;
	} writeback;

	union {
		struct dml2_dcn32x_soc_qos_params dcn32x;
		struct dml2_dcn4x_soc_qos_params dcn4x;
	} qos_params;

	enum dml2_qos_param_type qos_type;
};

struct dml2_soc_power_management_parameters {
	double dram_clk_change_blackout_us;
	double dram_clk_change_read_only_us; // deprecated
	double dram_clk_change_write_only_us; // deprecated
	double fclk_change_blackout_us;
	double g7_ppt_blackout_us;
	double g7_temperature_read_blackout_us;
	double stutter_enter_plus_exit_latency_us;
	double stutter_exit_latency_us;
	double low_power_stutter_enter_plus_exit_latency_us;
	double low_power_stutter_exit_latency_us;
	double z8_stutter_enter_plus_exit_latency_us;

Annotation

Implementation Notes