drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
Extension
.c
Size
773691 bytes
Lines
13430
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dml2_core_internal_g6_temp_read_blackouts_table {
	struct {
		unsigned int uclk_khz;
		unsigned int blackout_us;
	} entries[DML_MAX_CLK_TABLE_SIZE];
};

struct dml2_core_internal_g6_temp_read_blackouts_table core_dcn4_g6_temp_read_blackout_table = {
	.entries = {
		{
			.uclk_khz = 96000,
			.blackout_us = 23,
		},
		{
			.uclk_khz = 435000,
			.blackout_us = 10,
		},
		{
			.uclk_khz = 521000,
			.blackout_us = 10,
		},
		{
			.uclk_khz = 731000,
			.blackout_us = 8,
		},
		{
			.uclk_khz = 822000,
			.blackout_us = 8,
		},
		{
			.uclk_khz = 962000,
			.blackout_us = 5,
		},
		{
			.uclk_khz = 1069000,
			.blackout_us = 5,
		},
		{
			.uclk_khz = 1187000,
			.blackout_us = 5,
		},
	},
};

static double get_g6_temp_read_blackout_us(
	struct dml2_soc_bb *soc,
	unsigned int uclk_freq_khz,
	unsigned int min_clk_index)
{
	unsigned int i;
	unsigned int blackout_us = core_dcn4_g6_temp_read_blackout_table.entries[0].blackout_us;

	if (soc->power_management_parameters.g6_temp_read_blackout_us[0] > 0.0) {
		/* overrides are present in the SoC BB */
		return soc->power_management_parameters.g6_temp_read_blackout_us[min_clk_index];
	}

	/* use internal table */
	blackout_us = core_dcn4_g6_temp_read_blackout_table.entries[0].blackout_us;

	for (i = 0; i < DML_MAX_CLK_TABLE_SIZE; i++) {
		if (uclk_freq_khz < core_dcn4_g6_temp_read_blackout_table.entries[i].uclk_khz ||
			core_dcn4_g6_temp_read_blackout_table.entries[i].uclk_khz == 0) {
			break;
		}

		blackout_us = core_dcn4_g6_temp_read_blackout_table.entries[i].blackout_us;
	}

	return (double)blackout_us;
}

static double get_max_urgent_latency_us(
	struct dml2_dcn4x_soc_qos_params *dcn4x,
	double uclk_freq_mhz,
	double FabricClock,
	unsigned int min_clk_index)
{
	double latency;
	latency = dcn4x->per_uclk_dpm_params[min_clk_index].maximum_latency_when_urgent_uclk_cycles / uclk_freq_mhz
		* (1 + dcn4x->umc_max_latency_margin / 100.0)
		+ dcn4x->mall_overhead_fclk_cycles / FabricClock
		+ dcn4x->max_round_trip_to_furthest_cs_fclk_cycles / FabricClock
		* (1 + dcn4x->fabric_max_transport_latency_margin / 100.0);
	return latency;
}

static void calculate_pstate_keepout_dst_lines(
		const struct dml2_display_cfg *display_cfg,
		const struct dml2_core_internal_watermarks *watermarks,

Annotation

Implementation Notes