drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c
Extension
.c
Size
1028 bytes
Lines
46
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: MIT
//
// Copyright 2024 Advanced Micro Devices, Inc.

#include "dml2_mcg_factory.h"
#include "dml2_mcg_dcn4.h"
#include "dml2_mcg_dcn42.h"
#include "dml2_external_lib_deps.h"

static bool dummy_build_min_clock_table(struct dml2_mcg_build_min_clock_table_params_in_out *in_out)
{
	(void)in_out;
	return true;
}

bool dml2_mcg_create(enum dml2_project_id project_id, struct dml2_mcg_instance *out)
{
	bool result = false;

	if (!out)
		return false;

	memset(out, 0, sizeof(struct dml2_mcg_instance));

	switch (project_id) {
	case dml2_project_dcn4x_stage1:
		out->build_min_clock_table = &dummy_build_min_clock_table;
		result = true;
		break;
	case dml2_project_dcn4x_stage2:
	case dml2_project_dcn4x_stage2_auto_drr_svp:
		out->build_min_clock_table = &mcg_dcn4_build_min_clock_table;
		result = true;
		break;
	case dml2_project_dcn42:
		out->build_min_clock_table = &mcg_dcn42_build_min_clock_table;
		result = true;
		break;
	case dml2_project_invalid:
	default:
		break;
	}

	return result;
}

Annotation

Implementation Notes