drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h

Extension

.h

Size

29223 bytes

Lines

1015

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• dml2_external_lib_deps.h
• dml_top_types.h
• dml2_core_shared_types.h

Detected Declarations

• struct dram_bw_to_min_clk_table_entry
• struct dml2_mcg_dram_bw_to_min_clk_table
• struct dml2_mcg_min_clock_table
• struct dml2_mcg_build_min_clock_table_params_in_out
• struct dml2_mcg_instance
• struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out
• struct dml2_dpmm_map_watermarks_params_in_out
• struct dml2_dpmm_scratch
• struct dml2_dpmm_instance
• struct dml2_core_initialize_in_out
• struct core_bandwidth_requirements
• struct core_plane_support_info
• struct core_stream_support_info
• struct core_display_cfg_support_info
• struct dml2_core_mode_support_result
• struct dml2_optimization_stage1_state
• struct dml2_optimization_stage2_state
• struct dml2_implicit_svp_meta
• struct dml2_pstate_per_method_common_meta
• struct dml2_pstate_meta
• struct dml2_pmo_synchronized_timing_groups
• struct dml2_optimization_stage3_state
• struct dml2_optimization_stage4_state
• struct dml2_optimization_stage5_state
• struct display_configuation_with_meta
• struct dml2_pmo_pstate_strategy
• struct dml2_core_mode_support_in_out
• struct dml2_core_mode_programming_in_out
• struct dml2_core_populate_informative_in_out
• struct dml2_calculate_mcache_allocation_in_out
• struct dml2_core_internal_state_inputs
• struct dml2_core_internal_state_intermediates
• struct dml2_core_mode_support_locals
• struct dml2_core_mode_programming_locals
• struct dml2_core_scratch
• struct dml2_core_instance
• struct dml2_pmo_initialize_in_out
• struct dml2_pmo_optimize_dcc_mcache_in_out
• struct dml2_pmo_init_for_vmin_in_out
• struct dml2_pmo_test_for_vmin_in_out
• struct dml2_pmo_optimize_for_vmin_in_out
• struct dml2_pmo_init_for_pstate_support_in_out
• struct dml2_pmo_test_for_pstate_support_in_out
• struct dml2_pmo_optimize_for_pstate_support_in_out
• struct dml2_pmo_init_for_stutter_in_out
• struct dml2_pmo_test_for_stutter_in_out
• struct dml2_pmo_optimize_for_stutter_in_out
• struct dml2_scheduling_check_locals

Annotated Snippet

struct dram_bw_to_min_clk_table_entry {
	unsigned long long pre_derate_dram_bw_kbps;
	unsigned long min_uclk_khz;
	unsigned long min_fclk_khz;
	unsigned long min_dcfclk_khz;
};

struct dml2_mcg_dram_bw_to_min_clk_table {
	struct dram_bw_to_min_clk_table_entry entries[DML_MCG_MAX_CLK_TABLE_SIZE];

	unsigned int num_entries;
};

struct dml2_mcg_min_clock_table {
	struct {
		unsigned int dispclk;
		unsigned int dppclk;
		unsigned int dscclk;
		unsigned int dtbclk;
		unsigned int phyclk;
		unsigned int fclk;
		unsigned int dcfclk;
	} max_clocks_khz;

	struct {
		unsigned int dispclk;
		unsigned int dppclk;
		unsigned int dtbclk;
	} max_ss_clocks_khz;

	struct {
		unsigned int dprefclk;
		unsigned int xtalclk;
		unsigned int pcierefclk;
		unsigned int dchubrefclk;
		unsigned int amclk;
	} fixed_clocks_khz;

	struct dml2_mcg_dram_bw_to_min_clk_table dram_bw_table;
};

struct dml2_mcg_build_min_clock_table_params_in_out {
	/*
	* Input
	*/
	struct dml2_soc_bb *soc_bb;
	struct {
		bool perform_pseudo_build;
	} clean_me_up;

	/*
	* Output
	*/
	struct dml2_mcg_min_clock_table *min_clk_table;
};
struct dml2_mcg_instance {
	bool (*build_min_clock_table)(struct dml2_mcg_build_min_clock_table_params_in_out *in_out);
};

/*
* DML2 DPMM Types and Interfaces
*/

struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out {
	/*
	* Input
	*/
	struct dml2_core_ip_params *ip;
	struct dml2_soc_bb *soc_bb;
	struct dml2_mcg_min_clock_table *min_clk_table;
	const struct display_configuation_with_meta *display_cfg;
	struct {
		bool perform_pseudo_map;
		struct dml2_core_internal_soc_bb *soc_bb;
	} clean_me_up;

	/*
	* Output
	*/
	struct dml2_display_cfg_programming *programming;
};

struct dml2_dpmm_map_watermarks_params_in_out {
	/*
	* Input
	*/
	const struct display_configuation_with_meta *display_cfg;
	const struct dml2_core_instance *core;

	/*

Annotation

• Immediate include surface: `dml2_external_lib_deps.h`, `dml_top_types.h`, `dml2_core_shared_types.h`.
• Detected declarations: `struct dram_bw_to_min_clk_table_entry`, `struct dml2_mcg_dram_bw_to_min_clk_table`, `struct dml2_mcg_min_clock_table`, `struct dml2_mcg_build_min_clock_table_params_in_out`, `struct dml2_mcg_instance`, `struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out`, `struct dml2_dpmm_map_watermarks_params_in_out`, `struct dml2_dpmm_scratch`, `struct dml2_dpmm_instance`, `struct dml2_core_initialize_in_out`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.