drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
Extension: .h
Size: 65708 bytes
Lines: 1532
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

dpp.h

Detected Declarations

struct dcn_dpp_shift
struct dcn_dpp_mask
struct dcn_dpp_registers
struct dcn10_dpp
enum dcn10_input_csc_select

Annotated Snippet

struct dcn_dpp_shift {
	TF_REG_FIELD_LIST(uint8_t)
};

struct dcn_dpp_mask {
	TF_REG_FIELD_LIST(uint32_t)
};

#define DPP_COMMON_REG_VARIABLE_LIST \
	uint32_t DSCL_EXT_OVERSCAN_LEFT_RIGHT; \
	uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM; \
	uint32_t OTG_H_BLANK; \
	uint32_t OTG_V_BLANK; \
	uint32_t DSCL_MEM_PWR_CTRL; \
	uint32_t DSCL_MEM_PWR_STATUS; \
	uint32_t SCL_MODE; \
	uint32_t LB_DATA_FORMAT; \
	uint32_t LB_MEMORY_CTRL; \
	uint32_t DSCL_AUTOCAL; \
	uint32_t DSCL_CONTROL; \
	uint32_t SCL_BLACK_OFFSET; \
	uint32_t SCL_TAP_CONTROL; \
	uint32_t SCL_COEF_RAM_TAP_SELECT; \
	uint32_t SCL_COEF_RAM_TAP_DATA; \
	uint32_t DSCL_2TAP_CONTROL; \
	uint32_t MPC_SIZE; \
	uint32_t SCL_HORZ_FILTER_SCALE_RATIO; \
	uint32_t SCL_VERT_FILTER_SCALE_RATIO; \
	uint32_t SCL_HORZ_FILTER_SCALE_RATIO_C; \
	uint32_t SCL_VERT_FILTER_SCALE_RATIO_C; \
	uint32_t SCL_HORZ_FILTER_INIT; \
	uint32_t SCL_HORZ_FILTER_INIT_C; \
	uint32_t SCL_VERT_FILTER_INIT; \
	uint32_t SCL_VERT_FILTER_INIT_BOT; \
	uint32_t SCL_VERT_FILTER_INIT_C; \
	uint32_t SCL_VERT_FILTER_INIT_BOT_C; \
	uint32_t RECOUT_START; \
	uint32_t RECOUT_SIZE; \
	uint32_t CM_GAMUT_REMAP_CONTROL; \
	uint32_t CM_GAMUT_REMAP_C11_C12; \
	uint32_t CM_GAMUT_REMAP_C13_C14; \
	uint32_t CM_GAMUT_REMAP_C21_C22; \
	uint32_t CM_GAMUT_REMAP_C23_C24; \
	uint32_t CM_GAMUT_REMAP_C31_C32; \
	uint32_t CM_GAMUT_REMAP_C33_C34; \
	uint32_t CM_COMA_C11_C12; \
	uint32_t CM_COMA_C33_C34; \
	uint32_t CM_COMB_C11_C12; \
	uint32_t CM_COMB_C33_C34; \
	uint32_t CM_OCSC_CONTROL; \
	uint32_t CM_OCSC_C11_C12; \
	uint32_t CM_OCSC_C33_C34; \
	uint32_t CM_MEM_PWR_CTRL; \
	uint32_t CM_RGAM_LUT_DATA; \
	uint32_t CM_RGAM_LUT_WRITE_EN_MASK; \
	uint32_t CM_RGAM_LUT_INDEX; \
	uint32_t CM_RGAM_RAMB_START_CNTL_B; \
	uint32_t CM_RGAM_RAMB_START_CNTL_G; \
	uint32_t CM_RGAM_RAMB_START_CNTL_R; \
	uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B; \
	uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G; \
	uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R; \
	uint32_t CM_RGAM_RAMB_END_CNTL1_B; \
	uint32_t CM_RGAM_RAMB_END_CNTL2_B; \
	uint32_t CM_RGAM_RAMB_END_CNTL1_G; \
	uint32_t CM_RGAM_RAMB_END_CNTL2_G; \
	uint32_t CM_RGAM_RAMB_END_CNTL1_R; \
	uint32_t CM_RGAM_RAMB_END_CNTL2_R; \
	uint32_t CM_RGAM_RAMB_REGION_0_1; \
	uint32_t CM_RGAM_RAMB_REGION_32_33; \
	uint32_t CM_RGAM_RAMA_START_CNTL_B; \
	uint32_t CM_RGAM_RAMA_START_CNTL_G; \
	uint32_t CM_RGAM_RAMA_START_CNTL_R; \
	uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B; \
	uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G; \
	uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R; \
	uint32_t CM_RGAM_RAMA_END_CNTL1_B; \
	uint32_t CM_RGAM_RAMA_END_CNTL2_B; \
	uint32_t CM_RGAM_RAMA_END_CNTL1_G; \
	uint32_t CM_RGAM_RAMA_END_CNTL2_G; \
	uint32_t CM_RGAM_RAMA_END_CNTL1_R; \
	uint32_t CM_RGAM_RAMA_END_CNTL2_R; \
	uint32_t CM_RGAM_RAMA_REGION_0_1; \
	uint32_t CM_RGAM_RAMA_REGION_32_33; \
	uint32_t CM_RGAM_CONTROL; \
	uint32_t CM_CMOUT_CONTROL; \
	uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK; \
	uint32_t CM_BLNDGAM_CONTROL; \
	uint32_t CM_BLNDGAM_RAMB_START_CNTL_B; \
	uint32_t CM_BLNDGAM_RAMB_START_CNTL_G; \

Annotation

Immediate include surface: `dpp.h`.
Detected declarations: `struct dcn_dpp_shift`, `struct dcn_dpp_mask`, `struct dcn_dpp_registers`, `struct dcn10_dpp`, `enum dcn10_input_csc_select`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.