drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
Extension
.h
Size
47481 bytes
Lines
789
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dcn2_dpp_shift {
	TF_REG_FIELD_LIST_DCN2_0(uint8_t);
};

struct dcn2_dpp_mask {
	TF_REG_FIELD_LIST_DCN2_0(uint32_t);
};

#define DPP_DCN2_REG_VARIABLE_LIST \
	DPP_COMMON_REG_VARIABLE_LIST \
	uint32_t CM_BLNDGAM_LUT_DATA; \
	uint32_t ALPHA_2BIT_LUT; \
	uint32_t FCNV_FP_BIAS_R; \
	uint32_t FCNV_FP_BIAS_G; \
	uint32_t FCNV_FP_BIAS_B; \
	uint32_t FCNV_FP_SCALE_R; \
	uint32_t FCNV_FP_SCALE_G; \
	uint32_t FCNV_FP_SCALE_B; \
	uint32_t COLOR_KEYER_CONTROL; \
	uint32_t COLOR_KEYER_ALPHA; \
	uint32_t COLOR_KEYER_RED; \
	uint32_t COLOR_KEYER_GREEN; \
	uint32_t COLOR_KEYER_BLUE; \
	uint32_t OBUF_MEM_PWR_CTRL

#define DPP_DCN2_REG_VARIABLE_LIST_CM_APPEND \
	uint32_t CM_GAMUT_REMAP_B_C11_C12; \
	uint32_t CM_GAMUT_REMAP_B_C13_C14; \
	uint32_t CM_GAMUT_REMAP_B_C21_C22; \
	uint32_t CM_GAMUT_REMAP_B_C23_C24; \
	uint32_t CM_GAMUT_REMAP_B_C31_C32; \
	uint32_t CM_GAMUT_REMAP_B_C33_C34; \
	uint32_t CM_ICSC_B_C11_C12; \
	uint32_t CM_ICSC_B_C33_C34

struct dcn2_dpp_registers {
	DPP_DCN2_REG_VARIABLE_LIST;
	DPP_DCN2_REG_VARIABLE_LIST_CM_APPEND;
};

struct dcn20_dpp {
	struct dpp base;

	const struct dcn2_dpp_registers *tf_regs;
	const struct dcn2_dpp_shift *tf_shift;
	const struct dcn2_dpp_mask *tf_mask;

	const uint16_t *filter_v;
	const uint16_t *filter_h;
	const uint16_t *filter_v_c;
	const uint16_t *filter_h_c;
	int lb_pixel_depth_supported;
	int lb_memory_size;
	int lb_bits_per_entry;
	bool is_write_to_ram_a_safe;
	bool dispclk_r_gate_disable;
	struct scaler_data scl_data;
	struct pwl_params pwl_data;
};

enum dcn20_input_csc_select {
	DCN2_ICSC_SELECT_BYPASS = 0,
	DCN2_ICSC_SELECT_ICSC_A = 1,
	DCN2_ICSC_SELECT_ICSC_B = 2
};

enum dcn20_gamut_remap_select {
	DCN2_GAMUT_REMAP_BYPASS = 0,
	DCN2_GAMUT_REMAP_COEF_A = 1,
	DCN2_GAMUT_REMAP_COEF_B = 2
};

void dpp20_read_state(struct dpp *dpp_base,
		struct dcn_dpp_state *s);

void dpp2_set_degamma_pwl(
		struct dpp *dpp_base,
		const struct pwl_params *params);

void dpp2_set_degamma(
		struct dpp *dpp_base,
		enum ipp_degamma_mode mode);

void dpp2_cm_set_gamut_remap(
	struct dpp *dpp_base,
	const struct dpp_grph_csc_adjustment *adjust);

void dpp2_program_input_csc(
		struct dpp *dpp_base,
		enum dc_color_space color_space,

Annotation

Implementation Notes