drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
Extension
.c
Size
51684 bytes
Lines
1572
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (s->rgam_lut_mode) {
			REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &rgam_lut_mode);
			if (!rgam_lut_mode)
				s->rgam_lut_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B
		}
	}
}

void dpp30_read_reg_state(struct dpp *dpp_base, struct dcn_dpp_reg_state *dpp_reg_state)
{
	struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

	dpp_reg_state->recout_start = REG_READ(RECOUT_START);
	dpp_reg_state->recout_size = REG_READ(RECOUT_SIZE);
	dpp_reg_state->scl_horz_filter_scale_ratio = REG_READ(SCL_HORZ_FILTER_SCALE_RATIO);
	dpp_reg_state->scl_vert_filter_scale_ratio = REG_READ(SCL_VERT_FILTER_SCALE_RATIO);
	dpp_reg_state->scl_mode = REG_READ(SCL_MODE);
	dpp_reg_state->cm_control = REG_READ(CM_CONTROL);
	dpp_reg_state->dpp_control = REG_READ(DPP_CONTROL);
	dpp_reg_state->dscl_control = REG_READ(DSCL_CONTROL);
	dpp_reg_state->obuf_control = REG_READ(OBUF_CONTROL);
	dpp_reg_state->mpc_size = REG_READ(MPC_SIZE);
}

/*program post scaler scs block in dpp CM*/
void dpp3_program_post_csc(
		struct dpp *dpp_base,
		enum dc_color_space color_space,
		enum dcn10_input_csc_select input_select,
		const struct out_csc_color_matrix *tbl_entry)
{
	struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
	int i;
	int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix);
	const uint16_t *regval = NULL;
	uint32_t cur_select = 0;
	enum dcn10_input_csc_select select;
	struct color_matrices_reg gam_regs;

	if (input_select == INPUT_CSC_SELECT_BYPASS) {
		REG_SET(CM_POST_CSC_CONTROL, 0, CM_POST_CSC_MODE, 0);
		return;
	}

	if (tbl_entry == NULL) {
		for (i = 0; i < arr_size; i++)
			if (dpp_input_csc_matrix[i].color_space == color_space) {
				regval = dpp_input_csc_matrix[i].regval;
				break;
			}

		if (regval == NULL) {
			BREAK_TO_DEBUGGER();
			return;
		}
	} else {
		regval = tbl_entry->regval;
	}

	/* determine which CSC matrix (icsc or coma) we are using
	 * currently.  select the alternate set to double buffer
	 * the CSC update so CSC is updated on frame boundary
	 */
	REG_GET(CM_POST_CSC_CONTROL,
			CM_POST_CSC_MODE_CURRENT, &cur_select);

	if (cur_select != INPUT_CSC_SELECT_ICSC)
		select = INPUT_CSC_SELECT_ICSC;
	else
		select = INPUT_CSC_SELECT_COMA;

	gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11;
	gam_regs.masks.csc_c11  = dpp->tf_mask->CM_POST_CSC_C11;
	gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12;
	gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12;

	if (select == INPUT_CSC_SELECT_ICSC) {

		gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12);
		gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34);

	} else {

		gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12);
		gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34);

	}

	cm_helper_program_color_matrices(
			dpp->base.ctx,

Annotation

Implementation Notes