drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
Extension: .h
Size: 29010 bytes
Lines: 652
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

dcn20/dcn20_dpp.h

Detected Declarations

struct dcn3_dpp_shift
struct dcn3_dpp_mask
struct dcn3_dpp_registers
struct dcn3_dpp

Annotated Snippet

struct dcn3_dpp_shift {
	DPP_REG_FIELD_LIST_DCN3(uint8_t);
};

struct dcn3_dpp_mask {
	DPP_REG_FIELD_LIST_DCN3(uint32_t);
};

#define DPP_DCN3_REG_VARIABLE_LIST_COMMON \
	DPP_DCN2_REG_VARIABLE_LIST; \
	uint32_t CM_MEM_PWR_STATUS;\
	uint32_t CM_MEM_PWR_STATUS2;\
	uint32_t CM_MEM_PWR_CTRL2;\
	uint32_t CM_DEALPHA;\
	uint32_t CM_BIAS_CR_R;\
	uint32_t CM_BIAS_Y_G_CB_B;\
	uint32_t PRE_DEGAM;\
	uint32_t PRE_DEALPHA; \
	uint32_t PRE_REALPHA; \
	uint32_t PRE_CSC_MODE; \
	uint32_t PRE_CSC_C11_C12; \
	uint32_t PRE_CSC_C33_C34; \
	uint32_t PRE_CSC_B_C11_C12; \
	uint32_t PRE_CSC_B_C33_C34; \
	uint32_t CM_POST_CSC_CONTROL; \
	uint32_t CM_POST_CSC_C11_C12; \
	uint32_t CM_POST_CSC_C33_C34; \
	uint32_t CM_POST_CSC_B_C11_C12; \
	uint32_t CM_POST_CSC_B_C33_C34; \
	uint32_t CM_GAMUT_REMAP_B_C11_C12; \
	uint32_t CM_GAMUT_REMAP_B_C13_C14; \
	uint32_t CM_GAMUT_REMAP_B_C21_C22; \
	uint32_t CM_GAMUT_REMAP_B_C23_C24; \
	uint32_t CM_GAMUT_REMAP_B_C31_C32; \
	uint32_t CM_GAMUT_REMAP_B_C33_C34; \
	uint32_t CM_GAMCOR_CONTROL; \
	uint32_t CM_GAMCOR_LUT_CONTROL; \
	uint32_t CM_GAMCOR_LUT_INDEX; \
	uint32_t CM_GAMCOR_LUT_DATA; \
	uint32_t CM_GAMCOR_RAMB_START_CNTL_B; \
	uint32_t CM_GAMCOR_RAMB_START_CNTL_G; \
	uint32_t CM_GAMCOR_RAMB_START_CNTL_R; \
	uint32_t CM_GAMCOR_RAMB_START_SLOPE_CNTL_B; \
	uint32_t CM_GAMCOR_RAMB_START_SLOPE_CNTL_G; \
	uint32_t CM_GAMCOR_RAMB_START_SLOPE_CNTL_R; \
	uint32_t CM_GAMCOR_RAMB_END_CNTL1_B; \
	uint32_t CM_GAMCOR_RAMB_END_CNTL2_B; \
	uint32_t CM_GAMCOR_RAMB_END_CNTL1_G; \
	uint32_t CM_GAMCOR_RAMB_END_CNTL2_G; \
	uint32_t CM_GAMCOR_RAMB_END_CNTL1_R; \
	uint32_t CM_GAMCOR_RAMB_END_CNTL2_R; \
	uint32_t CM_GAMCOR_RAMB_REGION_0_1; \
	uint32_t CM_GAMCOR_RAMB_REGION_32_33; \
	uint32_t CM_GAMCOR_RAMB_OFFSET_B; \
	uint32_t CM_GAMCOR_RAMB_OFFSET_G; \
	uint32_t CM_GAMCOR_RAMB_OFFSET_R; \
	uint32_t CM_GAMCOR_RAMB_START_BASE_CNTL_B; \
	uint32_t CM_GAMCOR_RAMB_START_BASE_CNTL_G; \
	uint32_t CM_GAMCOR_RAMB_START_BASE_CNTL_R; \
	uint32_t CM_GAMCOR_RAMA_START_CNTL_B; \
	uint32_t CM_GAMCOR_RAMA_START_CNTL_G; \
	uint32_t CM_GAMCOR_RAMA_START_CNTL_R; \
	uint32_t CM_GAMCOR_RAMA_START_SLOPE_CNTL_B; \
	uint32_t CM_GAMCOR_RAMA_START_SLOPE_CNTL_G; \
	uint32_t CM_GAMCOR_RAMA_START_SLOPE_CNTL_R; \
	uint32_t CM_GAMCOR_RAMA_END_CNTL1_B; \
	uint32_t CM_GAMCOR_RAMA_END_CNTL2_B; \
	uint32_t CM_GAMCOR_RAMA_END_CNTL1_G; \
	uint32_t CM_GAMCOR_RAMA_END_CNTL2_G; \
	uint32_t CM_GAMCOR_RAMA_END_CNTL1_R; \
	uint32_t CM_GAMCOR_RAMA_END_CNTL2_R; \
	uint32_t CM_GAMCOR_RAMA_REGION_0_1; \
	uint32_t CM_GAMCOR_RAMA_REGION_32_33; \
	uint32_t CM_GAMCOR_RAMA_OFFSET_B; \
	uint32_t CM_GAMCOR_RAMA_OFFSET_G; \
	uint32_t CM_GAMCOR_RAMA_OFFSET_R; \
	uint32_t CM_GAMCOR_RAMA_START_BASE_CNTL_B; \
	uint32_t CM_GAMCOR_RAMA_START_BASE_CNTL_G; \
	uint32_t CM_GAMCOR_RAMA_START_BASE_CNTL_R; \
	uint32_t CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B; \
	uint32_t CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G; \
	uint32_t CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R; \
	uint32_t CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B; \
	uint32_t CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G; \
	uint32_t CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R; \
	uint32_t CM_BLNDGAM_LUT_CONTROL


struct dcn3_dpp_registers {
	DPP_DCN3_REG_VARIABLE_LIST_COMMON;

Annotation

Immediate include surface: `dcn20/dcn20_dpp.h`.
Detected declarations: `struct dcn3_dpp_shift`, `struct dcn3_dpp_mask`, `struct dcn3_dpp_registers`, `struct dcn3_dpp`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.