drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c
Extension
.c
Size
7435 bytes
Lines
245
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {
			cur_rom_en = 1;
		}
	}

	if (!dpp_base->cursor_offload)
		REG_UPDATE_3(CURSOR0_CONTROL,
			CUR0_MODE, color_format,
			CUR0_EXPANSION_MODE, 0,
			CUR0_ROM_EN, cur_rom_en);

	if (color_format == CURSOR_MODE_MONO) {
		/* todo: clarify what to program these to */

		if (!dpp_base->cursor_offload) {
			REG_UPDATE(CURSOR0_COLOR0,
				CUR0_COLOR0, 0x00000000);
			REG_UPDATE(CURSOR0_COLOR1,
				CUR0_COLOR1, 0xFFFFFFFF);
		}
	}

	dpp_base->att.cur0_ctl.bits.expansion_mode = 0;
	dpp_base->att.cur0_ctl.bits.cur0_rom_en = cur_rom_en;
	dpp_base->att.cur0_ctl.bits.mode = color_format;
}

void dpp401_set_cursor_position(
	struct dpp *dpp_base,
	const struct dc_cursor_position *pos,
	const struct dc_cursor_mi_param *param,
	uint32_t width,
	uint32_t height)
{
	(void)param;
	(void)width;
	(void)height;
	struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
	uint32_t cur_en = pos->enable ? 1 : 0;

	if (dpp_base->pos.cur0_ctl.bits.cur0_enable != cur_en) {
		if (!dpp_base->cursor_offload)
			REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en);
	}

	dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en;
	dpp_base->att.cur0_ctl.bits.cur0_enable = cur_en;
}

void dpp401_set_optional_cursor_attributes(
	struct dpp *dpp_base,
	struct dpp_cursor_attributes *attr)
{
	struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

	if (attr) {
		if (!dpp_base->cursor_offload) {
			REG_UPDATE(CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_BIAS_G_Y, attr->bias);
			REG_UPDATE(CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_SCALE_G_Y, attr->scale);
			REG_UPDATE(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_BIAS_RB_CRCB, attr->bias);
			REG_UPDATE(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_SCALE_RB_CRCB, attr->scale);
		}

		dpp_base->att.fp_scale_bias_g_y.bits.fp_bias_g_y = attr->bias;
		dpp_base->att.fp_scale_bias_g_y.bits.fp_scale_g_y = attr->scale;
		dpp_base->att.fp_scale_bias_rb_crcb.bits.fp_bias_rb_crcb = attr->bias;
		dpp_base->att.fp_scale_bias_rb_crcb.bits.fp_scale_rb_crcb = attr->scale;
	}
}

/* Program Cursor matrix block in DPP CM */
static void dpp401_program_cursor_csc(
	struct dpp *dpp_base,
	enum dc_color_space color_space,
	const struct dpp_input_csc_matrix *tbl_entry)
{
	struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
	uint32_t mode_select = 0;
	struct color_matrices_reg cur_matrix_regs;
	unsigned int i;
	const uint16_t *regval = NULL;
	unsigned int arr_size = sizeof(dpp_input_csc_matrix) / sizeof(struct dpp_input_csc_matrix);

	if (color_space < COLOR_SPACE_YCBCR601) {
		REG_SET(CUR0_MATRIX_MODE, 0, CUR0_MATRIX_MODE, CUR_MATRIX_BYPASS);
		return;
	}

	/* If adjustments not provided use hardcoded table for color space conversion */
	if (tbl_entry == NULL) {

Annotation

Implementation Notes