drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
Extension
.h
Size
27684 bytes
Lines
620
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dcn20_dsc_registers {
	uint32_t DSC_TOP_CONTROL;
	uint32_t DSC_DEBUG_CONTROL;
	uint32_t DSCC_CONFIG0;
	uint32_t DSCC_CONFIG1;
	uint32_t DSCC_STATUS;
	uint32_t DSCC_INTERRUPT_CONTROL_STATUS;
	uint32_t DSCC_PPS_CONFIG0;
	uint32_t DSCC_PPS_CONFIG1;
	uint32_t DSCC_PPS_CONFIG2;
	uint32_t DSCC_PPS_CONFIG3;
	uint32_t DSCC_PPS_CONFIG4;
	uint32_t DSCC_PPS_CONFIG5;
	uint32_t DSCC_PPS_CONFIG6;
	uint32_t DSCC_PPS_CONFIG7;
	uint32_t DSCC_PPS_CONFIG8;
	uint32_t DSCC_PPS_CONFIG9;
	uint32_t DSCC_PPS_CONFIG10;
	uint32_t DSCC_PPS_CONFIG11;
	uint32_t DSCC_PPS_CONFIG12;
	uint32_t DSCC_PPS_CONFIG13;
	uint32_t DSCC_PPS_CONFIG14;
	uint32_t DSCC_PPS_CONFIG15;
	uint32_t DSCC_PPS_CONFIG16;
	uint32_t DSCC_PPS_CONFIG17;
	uint32_t DSCC_PPS_CONFIG18;
	uint32_t DSCC_PPS_CONFIG19;
	uint32_t DSCC_PPS_CONFIG20;
	uint32_t DSCC_PPS_CONFIG21;
	uint32_t DSCC_PPS_CONFIG22;
	uint32_t DSCC_MEM_POWER_CONTROL;
	uint32_t DSCC_R_Y_SQUARED_ERROR_LOWER;
	uint32_t DSCC_R_Y_SQUARED_ERROR_UPPER;
	uint32_t DSCC_G_CB_SQUARED_ERROR_LOWER;
	uint32_t DSCC_G_CB_SQUARED_ERROR_UPPER;
	uint32_t DSCC_B_CR_SQUARED_ERROR_LOWER;
	uint32_t DSCC_B_CR_SQUARED_ERROR_UPPER;
	uint32_t DSCC_MAX_ABS_ERROR0;
	uint32_t DSCC_MAX_ABS_ERROR1;
	uint32_t DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL;
	uint32_t DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL;
	uint32_t DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL;
	uint32_t DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL;
	uint32_t DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL;
	uint32_t DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL;
	uint32_t DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL;
	uint32_t DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL;
	uint32_t DSCC_TEST_DEBUG_BUS_ROTATE;
	uint32_t DSCCIF_CONFIG0;
	uint32_t DSCCIF_CONFIG1;
	uint32_t DSCRM_DSC_FORWARD_CONFIG;
};


struct dcn20_dsc_shift {
	DSC_FIELD_LIST_DCN20(uint8_t);
};

struct dcn20_dsc_mask {
	DSC_FIELD_LIST_DCN20(uint32_t);
};

/* DSCCIF_CONFIG.INPUT_PIXEL_FORMAT values */
enum dsc_pixel_format {
	DSC_PIXFMT_RGB,
	DSC_PIXFMT_YCBCR444,
	DSC_PIXFMT_SIMPLE_YCBCR422,
	DSC_PIXFMT_NATIVE_YCBCR422,
	DSC_PIXFMT_NATIVE_YCBCR420,
	DSC_PIXFMT_UNKNOWN
};

struct dsc_reg_values {
	/* PPS registers */
	struct drm_dsc_config pps;

	/* Additional registers */
	uint32_t dsc_clock_enable;
	uint32_t dsc_clock_gating_disable;
	uint32_t underflow_recovery_en;
	uint32_t underflow_occurred_int_en;
	uint32_t underflow_occurred_status;
	enum dsc_pixel_format pixel_format;
	uint32_t ich_reset_at_eol;
	uint32_t alternate_ich_encoding_en;
	uint32_t num_slices_h;
	uint32_t num_slices_v;
	uint32_t rc_buffer_model_size;
	uint32_t disable_ich;
	uint32_t bpp_x32;

Annotation

Implementation Notes