drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
Extension: .h
Size: 19560 bytes
Lines: 347
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

dsc.h
dsc/dscc_types.h
dcn20/dcn20_dsc.h
drm/display/drm_dsc.h

Detected Declarations

struct dcn401_dsc_registers
struct dcn401_dsc_shift
struct dcn401_dsc_mask
struct dcn401_dsc

Annotated Snippet

struct dcn401_dsc_registers {
	uint32_t DSC_TOP_CONTROL;
	uint32_t DSC_DEBUG_CONTROL;
	uint32_t DSCC_CONFIG0;
	uint32_t DSCC_CONFIG1;
	uint32_t DSCC_STATUS;
	uint32_t DSCC_INTERRUPT_CONTROL0;
	uint32_t DSCC_INTERRUPT_CONTROL1;
	uint32_t DSCC_INTERRUPT_STATUS0;
	uint32_t DSCC_INTERRUPT_STATUS1;
	uint32_t DSCC_PPS_CONFIG0;
	uint32_t DSCC_PPS_CONFIG1;
	uint32_t DSCC_PPS_CONFIG2;
	uint32_t DSCC_PPS_CONFIG3;
	uint32_t DSCC_PPS_CONFIG4;
	uint32_t DSCC_PPS_CONFIG5;
	uint32_t DSCC_PPS_CONFIG6;
	uint32_t DSCC_PPS_CONFIG7;
	uint32_t DSCC_PPS_CONFIG8;
	uint32_t DSCC_PPS_CONFIG9;
	uint32_t DSCC_PPS_CONFIG10;
	uint32_t DSCC_PPS_CONFIG11;
	uint32_t DSCC_PPS_CONFIG12;
	uint32_t DSCC_PPS_CONFIG13;
	uint32_t DSCC_PPS_CONFIG14;
	uint32_t DSCC_PPS_CONFIG15;
	uint32_t DSCC_PPS_CONFIG16;
	uint32_t DSCC_PPS_CONFIG17;
	uint32_t DSCC_PPS_CONFIG18;
	uint32_t DSCC_PPS_CONFIG19;
	uint32_t DSCC_PPS_CONFIG20;
	uint32_t DSCC_PPS_CONFIG21;
	uint32_t DSCC_PPS_CONFIG22;
	uint32_t DSCC_MEM_POWER_CONTROL0;
	uint32_t DSCC_MEM_POWER_CONTROL1;
	uint32_t DSCC_R_Y_SQUARED_ERROR_LOWER;
	uint32_t DSCC_R_Y_SQUARED_ERROR_UPPER;
	uint32_t DSCC_G_CB_SQUARED_ERROR_LOWER;
	uint32_t DSCC_G_CB_SQUARED_ERROR_UPPER;
	uint32_t DSCC_B_CR_SQUARED_ERROR_LOWER;
	uint32_t DSCC_B_CR_SQUARED_ERROR_UPPER;
	uint32_t DSCC_MAX_ABS_ERROR0;
	uint32_t DSCC_MAX_ABS_ERROR1;
	uint32_t DSCC_TEST_DEBUG_BUS_ROTATE;
	uint32_t DSCCIF_CONFIG0;
	uint32_t DSCRM_DSC_FORWARD_CONFIG;
	uint32_t DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0;
	uint32_t DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1;
	uint32_t DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2;
	uint32_t DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3;
	uint32_t DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0;
	uint32_t DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1;
	uint32_t DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2;
	uint32_t DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3;
};

#define DSC_FIELD_LIST_DCN401(type)\
	DSC_FIELD_LIST_DCN20(type); \
	type DSC_FGCG_REP_DIS; \
	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0; \
	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1; \
	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2; \
	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3; \
	type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0; \
	type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1; \
	type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2; \
	type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3; \
	type DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0; \
	type DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1; \
	type DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2; \
	type DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3; \
	type DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED; \
	type DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0; \
	type DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1; \
	type DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2; \
	type DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3; \
	type DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0; \
	type DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1; \
	type DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2; \
	type DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3; \
	type DSCC_END_OF_FRAME_NOT_REACHED_CLEAR; \
	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0; \
	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1; \
	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2; \
	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3; \
	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0; \
	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1; \
	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2; \
	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3; \
	type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0; \

Annotation

Immediate include surface: `dsc.h`, `dsc/dscc_types.h`, `dcn20/dcn20_dsc.h`, `drm/display/drm_dsc.h`.
Detected declarations: `struct dcn401_dsc_registers`, `struct dcn401_dsc_shift`, `struct dcn401_dsc_mask`, `struct dcn401_dsc`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.