drivers/gpu/drm/amd/display/dc/dsc/dsc.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dsc/dsc.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dsc/dsc.h
Extension
.h
Size
4709 bytes
Lines
132
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dsc_config {
	uint32_t pic_width;
	uint32_t pic_height;
	enum dc_pixel_encoding pixel_encoding;
	enum dc_color_depth color_depth;  /* Bits per component */
	bool is_odm;
	struct dc_dsc_config dc_dsc_cfg;
	uint32_t dsc_padding;
};


/* Output parameters for configuring DSC-related part of OPTC */
struct dsc_optc_config {
	uint32_t slice_width; /* Slice width in pixels */
	uint32_t bytes_per_pixel; /* Bytes per pixel in u3.28 format */
	bool is_pixel_format_444; /* 'true' if pixel format is 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4)' */
};


struct dcn_dsc_state {
	uint32_t dsc_clock_en;
	uint32_t dsc_slice_width;
	uint32_t dsc_bits_per_pixel;
	uint32_t dsc_slice_height;
	uint32_t dsc_pic_width;
	uint32_t dsc_pic_height;
	uint32_t dsc_slice_bpg_offset;
	uint32_t dsc_chunk_size;
	uint32_t dsc_fw_en;
	uint32_t dsc_opp_source;
	uint32_t dsc_block_pred_enable;
	uint32_t dsc_line_buf_depth;
	uint32_t dsc_version_minor;
	uint32_t dsc_rc_buffer_size;
	uint32_t dsc_simple_422;
};

struct dcn_dsc_reg_state {
	uint32_t dsc_top_control;
	uint32_t dscc_interrupt_control_status;
};

/* DSC encoder capabilities
 * They differ from the DPCD DSC caps because they are based on AMD DSC encoder caps.
 */
union dsc_enc_slice_caps {
	struct {
		uint8_t NUM_SLICES_1 : 1;
		uint8_t NUM_SLICES_2 : 1;
		uint8_t NUM_SLICES_3 : 1; /* This one is not per DSC spec, but our encoder supports it */
		uint8_t NUM_SLICES_4 : 1;
		uint8_t NUM_SLICES_8 : 1;
		uint8_t NUM_SLICES_12 : 1;
		uint8_t NUM_SLICES_16 : 1;
	} bits;
	uint8_t raw;
};

struct dsc_enc_caps {
	uint8_t dsc_version;
	union dsc_enc_slice_caps slice_caps;
	int32_t lb_bit_depth;
	bool is_block_pred_supported;
	union dsc_color_formats color_formats;
	union dsc_color_depth color_depth;
	int32_t max_total_throughput_mps; /* Maximum total throughput with all the slices combined */
	int32_t max_slice_width;
	uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */
	bool is_frl;
	bool is_vic_all_bpp;
	uint32_t total_chunk_kbytes;
	uint32_t num_lanes;
	uint32_t frl_rate;
	uint32_t edp_sink_max_bits_per_pixel;
	bool is_dp;
};

struct dsc_funcs {
	void (*dsc_get_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);
	void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
	void (*dsc_read_reg_state)(struct display_stream_compressor *dsc, struct dcn_dsc_reg_state *dccg_reg_state);
	bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
	void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
			struct dsc_optc_config *dsc_optc_cfg);
	bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
			uint8_t *dsc_packed_pps);
	void (*dsc_enable)(struct display_stream_compressor *dsc, int opp_pipe);
	void (*dsc_disable)(struct display_stream_compressor *dsc);
	void (*dsc_disconnect)(struct display_stream_compressor *dsc);
	void (*dsc_wait_disconnect_pending_clear)(struct display_stream_compressor *dsc);

Annotation

Implementation Notes