drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
Extension: .h
Size: 46706 bytes
Lines: 920
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

struct dcn30_dwbc_registers
struct dcn30_dwbc_mask
struct dcn30_dwbc_shift
struct dcn30_dwbc
enum dwbscl_coef_filter_type_sel

Annotated Snippet

struct dcn30_dwbc_registers {
	/* DCN3AG */
	/* DWB_TOP */
	uint32_t DWB_ENABLE_CLK_CTRL;
	uint32_t DWB_MEM_PWR_CTRL;
	uint32_t FC_MODE_CTRL;
	uint32_t FC_FLOW_CTRL;
	uint32_t FC_WINDOW_START;
	uint32_t FC_WINDOW_SIZE;
	uint32_t FC_SOURCE_SIZE;
	uint32_t DWB_UPDATE_CTRL;
	uint32_t DWB_CRC_CTRL;
	uint32_t DWB_CRC_MASK_R_G;
	uint32_t DWB_CRC_MASK_B_A;
	uint32_t DWB_CRC_VAL_R_G;
	uint32_t DWB_CRC_VAL_B_A;
	uint32_t DWB_OUT_CTRL;
	uint32_t DWB_MMHUBBUB_BACKPRESSURE_CNT_EN;
	uint32_t DWB_MMHUBBUB_BACKPRESSURE_CNT;
	uint32_t DWB_HOST_READ_CONTROL;
	uint32_t DWB_SOFT_RESET;
	uint32_t DWB_DEBUG_CTRL;
	uint32_t DWB_DEBUG;
	uint32_t DWB_TEST_DEBUG_INDEX;
	uint32_t DWB_TEST_DEBUG_DATA;

	/* DWBSCL */
	uint32_t DWBSCL_COEF_RAM_TAP_SELECT;
	uint32_t DWBSCL_COEF_RAM_TAP_DATA;
	uint32_t DWBSCL_MODE;
	uint32_t DWBSCL_TAP_CONTROL;
	uint32_t DWBSCL_HORZ_FILTER_SCALE_RATIO;
	uint32_t DWBSCL_HORZ_FILTER_INIT;
	uint32_t DWBSCL_VERT_FILTER_SCALE_RATIO;
	uint32_t DWBSCL_VERT_FILTER_INIT;
	uint32_t DWBSCL_BOUNDARY_CTRL;
	uint32_t DWBSCL_DEST_SIZE;
	uint32_t DWBSCL_OVERFLOW_STATUS;
	uint32_t DWBSCL_OVERFLOW_COUNTER;
	uint32_t DWBSCL_DEBUG;
	uint32_t DWBSCL_TEST_DEBUG_INDEX;
	uint32_t DWBSCL_TEST_DEBUG_DATA;

	/* DWBCP */
	uint32_t DWB_HDR_MULT_COEF;
	uint32_t DWB_GAMUT_REMAP_MODE;
	uint32_t DWB_GAMUT_REMAP_COEF_FORMAT;
	uint32_t DWB_GAMUT_REMAPA_C11_C12;
	uint32_t DWB_GAMUT_REMAPA_C13_C14;
	uint32_t DWB_GAMUT_REMAPA_C21_C22;
	uint32_t DWB_GAMUT_REMAPA_C23_C24;
	uint32_t DWB_GAMUT_REMAPA_C31_C32;
	uint32_t DWB_GAMUT_REMAPA_C33_C34;
	uint32_t DWB_GAMUT_REMAPB_C11_C12;
	uint32_t DWB_GAMUT_REMAPB_C13_C14;
	uint32_t DWB_GAMUT_REMAPB_C21_C22;
	uint32_t DWB_GAMUT_REMAPB_C23_C24;
	uint32_t DWB_GAMUT_REMAPB_C31_C32;
	uint32_t DWB_GAMUT_REMAPB_C33_C34;
	uint32_t DWB_OGAM_CONTROL;
	uint32_t DWB_OGAM_LUT_INDEX;
	uint32_t DWB_OGAM_LUT_DATA;
	uint32_t DWB_OGAM_LUT_CONTROL;
	uint32_t DWB_OGAM_RAMA_START_CNTL_B;
	uint32_t DWB_OGAM_RAMA_START_CNTL_G;
	uint32_t DWB_OGAM_RAMA_START_CNTL_R;
	uint32_t DWB_OGAM_RAMA_START_BASE_CNTL_B;
	uint32_t DWB_OGAM_RAMA_START_SLOPE_CNTL_B;
	uint32_t DWB_OGAM_RAMA_START_BASE_CNTL_G;
	uint32_t DWB_OGAM_RAMA_START_SLOPE_CNTL_G;
	uint32_t DWB_OGAM_RAMA_START_BASE_CNTL_R;
	uint32_t DWB_OGAM_RAMA_START_SLOPE_CNTL_R;
	uint32_t DWB_OGAM_RAMA_END_CNTL1_B;
	uint32_t DWB_OGAM_RAMA_END_CNTL2_B;
	uint32_t DWB_OGAM_RAMA_END_CNTL1_G;
	uint32_t DWB_OGAM_RAMA_END_CNTL2_G;
	uint32_t DWB_OGAM_RAMA_END_CNTL1_R;
	uint32_t DWB_OGAM_RAMA_END_CNTL2_R;
	uint32_t DWB_OGAM_RAMA_OFFSET_B;
	uint32_t DWB_OGAM_RAMA_OFFSET_G;
	uint32_t DWB_OGAM_RAMA_OFFSET_R;
	uint32_t DWB_OGAM_RAMA_REGION_0_1;
	uint32_t DWB_OGAM_RAMA_REGION_2_3;
	uint32_t DWB_OGAM_RAMA_REGION_4_5;
	uint32_t DWB_OGAM_RAMA_REGION_6_7;
	uint32_t DWB_OGAM_RAMA_REGION_8_9;
	uint32_t DWB_OGAM_RAMA_REGION_10_11;
	uint32_t DWB_OGAM_RAMA_REGION_12_13;
	uint32_t DWB_OGAM_RAMA_REGION_14_15;
	uint32_t DWB_OGAM_RAMA_REGION_16_17;

Annotation

Detected declarations: `struct dcn30_dwbc_registers`, `struct dcn30_dwbc_mask`, `struct dcn30_dwbc_shift`, `struct dcn30_dwbc`, `enum dwbscl_coef_filter_type_sel`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.