drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c- Extension
.c- Size
- 4646 bytes
- Lines
- 176
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dm_services.hinclude/gpio_types.h../hw_factory.hhw_factory_dce80.h../hw_gpio.h../hw_ddc.h../hw_hpd.h../hw_generic.hdce/dce_8_0_d.hdce/dce_8_0_sh_mask.hreg_helper.h../hpd_regs.h../ddc_regs.h
Detected Declarations
function define_ddc_registersfunction define_hpd_registersfunction dal_hw_factory_dce80_init
Annotated Snippet
#include "dm_services.h"
#include "include/gpio_types.h"
#include "../hw_factory.h"
#include "hw_factory_dce80.h"
#include "../hw_gpio.h"
#include "../hw_ddc.h"
#include "../hw_hpd.h"
#include "../hw_generic.h"
#include "dce/dce_8_0_d.h"
#include "dce/dce_8_0_sh_mask.h"
#define REG(reg_name)\
mm ## reg_name
#include "reg_helper.h"
#include "../hpd_regs.h"
#define HPD_REG_LIST_DCE8(id) \
HPD_GPIO_REG_LIST(id), \
.int_status = mmDC_HPD ## id ## _INT_STATUS,\
.toggle_filt_cntl = mmDC_HPD ## id ## _TOGGLE_FILT_CNTL
#define HPD_MASK_SH_LIST_DCE8(mask_sh) \
.DC_HPD_SENSE_DELAYED = DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED ## mask_sh,\
.DC_HPD_SENSE = DC_HPD1_INT_STATUS__DC_HPD1_SENSE ## mask_sh,\
.DC_HPD_CONNECT_INT_DELAY = DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY ## mask_sh,\
.DC_HPD_DISCONNECT_INT_DELAY = DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY ## mask_sh
#define hpd_regs(id) \
{\
HPD_REG_LIST_DCE8(id)\
}
static const struct hpd_registers hpd_regs[] = {
hpd_regs(1),
hpd_regs(2),
hpd_regs(3),
hpd_regs(4),
hpd_regs(5),
hpd_regs(6)
};
static const struct hpd_sh_mask hpd_shift = {
HPD_MASK_SH_LIST_DCE8(__SHIFT)
};
static const struct hpd_sh_mask hpd_mask = {
HPD_MASK_SH_LIST_DCE8(_MASK)
};
#include "../ddc_regs.h"
/* set field name */
#define SF_DDC(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
static const struct ddc_registers ddc_data_regs[] = {
ddc_data_regs(1),
ddc_data_regs(2),
ddc_data_regs(3),
ddc_data_regs(4),
ddc_data_regs(5),
ddc_data_regs(6),
ddc_vga_data_regs,
ddc_i2c_data_regs
};
static const struct ddc_registers ddc_clk_regs[] = {
ddc_clk_regs(1),
ddc_clk_regs(2),
ddc_clk_regs(3),
ddc_clk_regs(4),
ddc_clk_regs(5),
ddc_clk_regs(6),
ddc_vga_clk_regs,
ddc_i2c_clk_regs
};
static const struct ddc_sh_mask ddc_shift = {
DDC_MASK_SH_LIST(__SHIFT)
};
static const struct ddc_sh_mask ddc_mask = {
DDC_MASK_SH_LIST(_MASK)
};
Annotation
- Immediate include surface: `dm_services.h`, `include/gpio_types.h`, `../hw_factory.h`, `hw_factory_dce80.h`, `../hw_gpio.h`, `../hw_ddc.h`, `../hw_hpd.h`, `../hw_generic.h`.
- Detected declarations: `function define_ddc_registers`, `function define_hpd_registers`, `function dal_hw_factory_dce80_init`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.